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Re: [PATCH 09/16] x86/intel: Always check MSR_MISC_ENABLE on all CPUs
- To: Jan Beulich <jbeulich@xxxxxxxx>
- From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- Date: Tue, 27 Jan 2026 15:21:10 +0000
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- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>, Julian Vetter <julian.vetter@xxxxxxxxxx>, Teddy Astie <teddy.astie@xxxxxxxxxx>, Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Tue, 27 Jan 2026 15:21:23 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 27/01/2026 3:18 pm, Jan Beulich wrote:
> On 26.01.2026 18:53, Andrew Cooper wrote:
>> Currently, the BSP only leaves instructions for the APs to adjust
>> MSR_MISC_ENABLE if the BSP is found to need adjustments. Particularly if
>> XD_DISABLE is needed on an AP but not the BSP, the system will triple fault
>> with no information provided to the user.
>>
>> Rework the BSP and trampoline logic to always read MISC_ENABLE, and clear
>> CPUID_LIMIT and XD_DISABLE if either are set.
>>
>> Repurpose intel_unlock_cpuid_leaves() to be intel_check_misc_enable() and
>> make
>> it static in common.c.
> Being able to make it static is of course nice. But moving Intel-only code
> out of intel.c isn't. Personally I'd favor it staying in intel.c.
Alejandro's DCE work will cause this to be eliminated in !INTEL builds.
It's slightly ugly, but it's less ugly than having 3 separate hooks.
~Andrew
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