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Re: [PATCH 09/16] x86/intel: Always check MSR_MISC_ENABLE on all CPUs
- To: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- From: Jan Beulich <jbeulich@xxxxxxxx>
- Date: Tue, 27 Jan 2026 16:18:30 +0100
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- Cc: Roger Pau Monné <roger.pau@xxxxxxxxxx>, Julian Vetter <julian.vetter@xxxxxxxxxx>, Teddy Astie <teddy.astie@xxxxxxxxxx>, Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Tue, 27 Jan 2026 15:18:43 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 26.01.2026 18:53, Andrew Cooper wrote:
> Currently, the BSP only leaves instructions for the APs to adjust
> MSR_MISC_ENABLE if the BSP is found to need adjustments. Particularly if
> XD_DISABLE is needed on an AP but not the BSP, the system will triple fault
> with no information provided to the user.
>
> Rework the BSP and trampoline logic to always read MISC_ENABLE, and clear
> CPUID_LIMIT and XD_DISABLE if either are set.
>
> Repurpose intel_unlock_cpuid_leaves() to be intel_check_misc_enable() and make
> it static in common.c.
Being able to make it static is of course nice. But moving Intel-only code
out of intel.c isn't. Personally I'd favor it staying in intel.c.
Jan
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