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Re: [PATCH v1 06/14] xen/riscv: introduce exception context
- To: Oleksii <oleksii.kurochko@xxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Andrew Cooper <Andrew.Cooper3@xxxxxxxxxx>
- Date: Mon, 23 Jan 2023 12:25:09 +0000
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- Thread-topic: [PATCH v1 06/14] xen/riscv: introduce exception context
On 23/01/2023 12:03 pm, Oleksii wrote:
> On Fri, 2023-01-20 at 15:54 +0000, Andrew Cooper wrote:
>> On 20/01/2023 2:59 pm, Oleksii Kurochko wrote:
>>> +
>>> +#define RISCV_CPU_USER_REGS_OFFSET(x) ((RISCV_CPU_USER_REGS_##x)
>>> * __SIZEOF_POINTER__)
>>> +#define RISCV_CPU_USER_REGS_SIZE
>>> RISCV_CPU_USER_REGS_OFFSET(last)
>>> +
>>> +#ifndef __ASSEMBLY__
>>> +
>>> +/* On stack VCPU state */
>>> +struct cpu_user_regs
>>> +{
>>> + register_t zero;
>> unsigned long.
> Why is it better to define them as \unsigned long' instead of
> register_t?
Because there is a material cost to deliberately hiding the type, in
terms of code clarity and legibility.
Things like register_t and vaddr_t are nonsense in a POSIX-y build
environment where these things are spelled "unsigned long", not to
mention that the associated infrastructure is longer than the
non-obfuscated form.
~Andrew
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