[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [PATCH v1 06/14] xen/riscv: introduce exception context
- To: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Andrew Cooper <Andrew.Cooper3@xxxxxxxxxx>
- Date: Fri, 20 Jan 2023 15:54:44 +0000
- Accept-language: en-GB, en-US
- Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=citrix.com; dmarc=pass action=none header.from=citrix.com; dkim=pass header.d=citrix.com; arc=none
- Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6kU454m2W3k+QEM9kV0wYwdUPDVwotb1yhUhbg/UduM=; b=BpRyhF3o1dfdBeKq4fuvBsvkFN3osayOhzhnLYdfvqin1nbYeXHCz+CYhrnVOla8GU/oAksy2TpFGIZhTk2NmDJJl1xrQ0HR0fO0iusyqrE8ucJtuMW/sO8GqXW+q3PoKBUWygIDlHGjHm/MYCkUL2NgmwRFHHlSgmE4DJPpnfcuKmGXWEFDpXw/E/t0mud9mA7fSxcSkuUZ3v1SuDYNpYYlOi8+Htsyb6isVMA2HfxE5kVy3NCeQ/7iFxcakYBUSPemOTQSsqaYJBe4bqllyesVuRqerYY+H2mi9t7gu/AxT/qwhHsqZl3wCcJM+glJLBez+KIpwpDVQs+q+soDhw==
- Arc-seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=e/jcMW/jv+T56ehPQQySEXd9XMspUEmOpEu22zxQ4AzFS7MM5xe4n2UNMe2t3ljTdIo6iZGD9c9+gSh10fiPOc+XsxcAVHJEzJmcJstJbiSSH14dWqJ+FZLgkrLPp8zitM0Z9nTQ1q8GzdHP9MC7B3NuXgFchWrJhefuxJO2JNGVWtFFUNwM0+IY/YoxdtaqxE7HAwXB3J9nJ5KTkdCc12RHGolHQ9d6sSPv21TixkV7+cQ3rBZc8na+InWJSLz4HYv4x63ruYfH+c3lLnzLx7zFCC5tbXJVrX3iEk/xRVIkb54VPHAUZlVwsd354IZb5TX5E47a6cYluCqKUiKbbQ==
- Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=citrix.com;
- Cc: Stefano Stabellini <sstabellini@xxxxxxxxxx>, Gianluca Guida <gianluca@xxxxxxxxxxxx>, Bob Eshleman <bobbyeshleman@xxxxxxxxx>, Alistair Francis <alistair.francis@xxxxxxx>, Connor Davis <connojdavis@xxxxxxxxx>, Bobby Eshleman <bobby.eshleman@xxxxxxxxx>
- Delivery-date: Fri, 20 Jan 2023 15:55:05 +0000
- Ironport-data: A9a23:pQ0HraNdkogtozHvrR0WlsFynXyQoLVcMsEvi/4bfWQNrUp3hTQHy mBODG3Qa/6KYzb2fIoka96z8BwP6JTXydQxQQto+SlhQUwRpJueD7x1DKtS0wC6dZSfER09v 63yTvGacajYm1eF/k/F3oDJ9CU6jufQA+KmU4YoAwgpLSd8UiAtlBl/rOAwh49skLCRDhiE/ Nj/uKUzAnf8s9JPGj9Suv3rRC9H5qyo42tB5ARmP5ingXeF/5UrJMNHTU2OByOQrrl8RoaSW +vFxbelyWLVlz9F5gSNy+uTnuUiG9Y+DCDW4pZkc/HKbitq/0Te5p0TJvsEAXq7vh3S9zxHJ HehgrTrIeshFvWkdO3wyHC0GQkmVUFN0OevzXRSLaV/ZqAJGpfh66wGMa04AWEX0uNIKlhI9 aQ+EyIEalOz3KGM6+6ne/Y506zPLOGzVG8ekldJ6GmFSNwAEdXESaiM4sJE1jAtgMwIBezZe 8cSdTtoalLHfgFLPVAUTpk5mY9EhFGmK2Ee9A3T+vZxvzO7IA9ZidABNPL8fNCQSNoTtUGfv m/cpEzyAw0ANczZwj2Amp6prr6UwHulB9lNfFG+3uZJ32/K534OMTQHUWaBnuaG0lyaeN0Kf iT4/QJr98De7neDSd3wXAa5oTiHowQbUNpTFMU17QiMzuzf5APxLngJSHtNZcIrsOcyRCc2z RmZktXxHzttvbaJD3WH+d+8tiiuMCIYKWsDYy4sTgYf5dTn5oYpgXrnQddqFqqohdTdAzDux CuLqiN4jLIW5eYB0K+x7F3cgzaho5HPZgEw7wTTGGmi62tRbYqkfJCh6EKd4+xJKo2YVXGes HNCkM+bhMgFCpeLky6BSfsMB5mm4v+ENHvXhlsHN5Mm/T68vXO4fYRd5Th4DEhsO8cAPzTuZ SfuVRh54ZZSOD6ga/9xaofpV8Ayl/C8TpLiS+zeacdIbt5pbgib8SpyZEmWmWfwjEwrlqJ5M pCeGSqxMUsn5W1c5GLeb48gPXUDn0jSGUu7qUjH8ima
- Ironport-hdrordr: A9a23:xrfYI6HB77tHl1JApLqFwJLXdLJyesId70hD6qkvc3Fom52j/f xGws5x6fatskdrZJkh8erwW5Vp2RvnhNNICPoqTM2ftW7dySeVxeBZnMHfKljbdxEWmdQtsp uIH5IeNDS0NykDsS+Y2nj2Lz9D+qjgzEnAv463oBlQpENRGthdBmxCe2Sm+zhNNW177O0CZf +hD6R8xwaISDAyVICWF3MFV+/Mq5nik4/nWwcPA1oK+RSDljSh7Z/9Cly90g0FWz1C7L8++S yd+jaJp5mLgrWe8FvxxmXT55NZlJ/IzcZCPtWFjow4OyjhkQGhYaVmQvmnsCouqO+ixV42mJ 3nogsmPe5093TNF1vF7yfF6k3F6nID+nXiwViXjT/IusriXg83DMJHmMZwbgbZw1BIhqA+7I t7m0ai87ZHBxLJmyrwo/LSUQtxq0ayqX0+1cYOkn1kV5cEYrM5l/1cwKoVKuZEIMvJ0vFhLA BcNrCb2B+QSyLCU5nthBgq/DVrZAVqIv7JeDlYhiXf6UkqoJkw9Tpl+CVYpAZByHt1ceg72w yPWJ4Y641mX4sYa7lwC/wGRtbyAmvRQQjUOGbXOlj/ErobUki94qIfzY9Fk91CQqZ4uqcaid DEShdVpGQyc0XhBYmH24BK6AnERCG4US72ws9T6pBlsvmkLYCbehGrWRQriY+tsv8fCsrUV7 K6P49XGebqKS/rFZxS1wPzVpFOIT0VUdETuNw8R1WSy/i7YrHCp6jearLeNbDtGTErVif2BW YCRiH6IIFa4kWiShbD8WzssrPWCznCFL5LYdvnFrIoufkw36V3w3gooEX84N2XIjtftaFzdF diIdrc49GGmVU=
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Thread-index: AQHZLOAEizmhskK0b0Wez8lGfG74vK6ndUcA
- Thread-topic: [PATCH v1 06/14] xen/riscv: introduce exception context
On 20/01/2023 2:59 pm, Oleksii Kurochko wrote:
> diff --git a/xen/arch/riscv/include/asm/processor.h
> b/xen/arch/riscv/include/asm/processor.h
> new file mode 100644
> index 0000000000..5898a09ce6
> --- /dev/null
> +++ b/xen/arch/riscv/include/asm/processor.h
> @@ -0,0 +1,114 @@
> +/* SPDX-License-Identifier: MIT */
> +/******************************************************************************
> + *
> + * Copyright 2019 (C) Alistair Francis <alistair.francis@xxxxxxx>
> + * Copyright 2021 (C) Bobby Eshleman <bobby.eshleman@xxxxxxxxx>
> + * Copyright 2023 (C) Vates
> + *
> + */
> +
> +#ifndef _ASM_RISCV_PROCESSOR_H
> +#define _ASM_RISCV_PROCESSOR_H
> +
> +#include <asm/types.h>
> +
> +#define RISCV_CPU_USER_REGS_zero 0
> +#define RISCV_CPU_USER_REGS_ra 1
> +#define RISCV_CPU_USER_REGS_sp 2
> +#define RISCV_CPU_USER_REGS_gp 3
> +#define RISCV_CPU_USER_REGS_tp 4
> +#define RISCV_CPU_USER_REGS_t0 5
> +#define RISCV_CPU_USER_REGS_t1 6
> +#define RISCV_CPU_USER_REGS_t2 7
> +#define RISCV_CPU_USER_REGS_s0 8
> +#define RISCV_CPU_USER_REGS_s1 9
> +#define RISCV_CPU_USER_REGS_a0 10
> +#define RISCV_CPU_USER_REGS_a1 11
> +#define RISCV_CPU_USER_REGS_a2 12
> +#define RISCV_CPU_USER_REGS_a3 13
> +#define RISCV_CPU_USER_REGS_a4 14
> +#define RISCV_CPU_USER_REGS_a5 15
> +#define RISCV_CPU_USER_REGS_a6 16
> +#define RISCV_CPU_USER_REGS_a7 17
> +#define RISCV_CPU_USER_REGS_s2 18
> +#define RISCV_CPU_USER_REGS_s3 19
> +#define RISCV_CPU_USER_REGS_s4 20
> +#define RISCV_CPU_USER_REGS_s5 21
> +#define RISCV_CPU_USER_REGS_s6 22
> +#define RISCV_CPU_USER_REGS_s7 23
> +#define RISCV_CPU_USER_REGS_s8 24
> +#define RISCV_CPU_USER_REGS_s9 25
> +#define RISCV_CPU_USER_REGS_s10 26
> +#define RISCV_CPU_USER_REGS_s11 27
> +#define RISCV_CPU_USER_REGS_t3 28
> +#define RISCV_CPU_USER_REGS_t4 29
> +#define RISCV_CPU_USER_REGS_t5 30
> +#define RISCV_CPU_USER_REGS_t6 31
> +#define RISCV_CPU_USER_REGS_sepc 32
> +#define RISCV_CPU_USER_REGS_sstatus 33
> +#define RISCV_CPU_USER_REGS_pregs 34
> +#define RISCV_CPU_USER_REGS_last 35
This block wants moving into the asm-offsets infrastructure, but I
suspect they won't want to survive in this form.
edit: yeah, definitely not this form. RISCV_CPU_USER_REGS_OFFSET is a
recipe for bugs.
> +
> +#define RISCV_CPU_USER_REGS_OFFSET(x) ((RISCV_CPU_USER_REGS_##x) *
> __SIZEOF_POINTER__)
> +#define RISCV_CPU_USER_REGS_SIZE RISCV_CPU_USER_REGS_OFFSET(last)
> +
> +#ifndef __ASSEMBLY__
> +
> +/* On stack VCPU state */
> +struct cpu_user_regs
> +{
> + register_t zero;
unsigned long.
> + register_t ra;
> + register_t sp;
> + register_t gp;
> + register_t tp;
> + register_t t0;
> + register_t t1;
> + register_t t2;
> + register_t s0;
> + register_t s1;
> + register_t a0;
> + register_t a1;
> + register_t a2;
> + register_t a3;
> + register_t a4;
> + register_t a5;
> + register_t a6;
> + register_t a7;
> + register_t s2;
> + register_t s3;
> + register_t s4;
> + register_t s5;
> + register_t s6;
> + register_t s7;
> + register_t s8;
> + register_t s9;
> + register_t s10;
> + register_t s11;
> + register_t t3;
> + register_t t4;
> + register_t t5;
> + register_t t6;
> + register_t sepc;
> + register_t sstatus;
> + /* pointer to previous stack_cpu_regs */
> + register_t pregs;
Stale comment? Also, surely this wants to be cpu_user_regs *pregs; ?
> +};
> +
> +static inline void wait_for_interrupt(void)
There's no point writing out the name in longhand for a wrapper around a
single instruction.
~Andrew
|