Re: [Xen-devel] Interrupt injection with ISR set on Intel hardware

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 29.10.18 at 18:06, <andrew.cooper3@xxxxxxxxxx> wrote:
> On 29/10/18 16:58, Jan Beulich wrote:
>>>>> On 29.10.18 at 17:44, <andrew.cooper3@xxxxxxxxxx> wrote:
>>> On 29/10/18 16:33, Jan Beulich wrote:
>>>>>>> On 15.10.18 at 12:30, <roger.pau@xxxxxxxxxx> wrote:
>>>>> (XEN)   [22641] PUSH     {sp  0, irq  30, vec 0x21}
>>>> This is the last push or pop.
>>>>
>>>>> (XEN)   [22650] WAKE     PPR 0x00000020
>>>>> (XEN)                    IRR 
>>> 0000000002000000000000000000000000000000000000000000000000000000
>>>>> (XEN)                    ISR 
>>> 0000000002000000000000000000000000000000000000000000000000000000
>>>> For one I'm having trouble understanding why IRR here is different
>>>> from ...
>>>>
>>>>> (XEN) All LAPIC state:
>>>>> (XEN)   [vector]      ISR      TMR      IRR
>>>>> (XEN)   [1f:00]  00000000 00000000 00000000
>>>>> (XEN)   [3f:20]  00000002 00000000 00000000
>>>>> (XEN)   [5f:40]  00000000 00000000 00000000
>>>>> (XEN)   [7f:60]  00000000 00000000 00000000
>>>>> (XEN)   [9f:80]  00000000 00000000 00000000
>>>>> (XEN)   [bf:a0]  00000000 00000000 00000000
>>>>> (XEN)   [df:c0]  00000000 00000000 00000000
>>>>> (XEN)   [ff:e0]  00000000 00000000 04000000
>>>> ... IRR here.
>>> You shouldn't expect them to be the same.
>>>
>>> The WAKE line is sampled before we enable interrupts, and the "All LAPIC
>>> state" is after we enable interrupts and (erroneously) accept vector
>>> 0x21 a second time.
>> Oh, right - I had overlooked that the debugging patch was actually
>> attached to Roger's mail.
>>
>>> In the meantime, a TLB flush has become pending, but interrupts are
>>> currently disabled so it has yet to be accepted.  Remember that bits
>>> accumulate in IRR entirely asynchronously.
>> Well, bits newly set are of course to be expected at any time. My
>> issue was just with bit 0x21 having got cleared.
> 
> What is unexpected about that?
> 
> Accepting a vector clears it out of IRR and sets it in ISR.  A second
> interrupt can then be queued in IRR while the first is being serviced.

"Unexpected" was meant in the sense of how the sequence of
logged lines looked, without having looked at how the debugging
patch actually produces them.

Jan



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