Re: [Xen-devel] Interrupt injection with ISR set on Intel hardware

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 15.10.18 at 12:30, <roger.pau@xxxxxxxxxx> wrote:
> (XEN)   [22641] PUSH     {sp  0, irq  30, vec 0x21}

This is the last push or pop.

> (XEN)   [22650] WAKE     PPR 0x00000020
> (XEN)                    IRR 
> 0000000002000000000000000000000000000000000000000000000000000000
> (XEN)                    ISR 
> 0000000002000000000000000000000000000000000000000000000000000000

For one I'm having trouble understanding why IRR here is different
from ...

> (XEN) All LAPIC state:
> (XEN)   [vector]      ISR      TMR      IRR
> (XEN)   [1f:00]  00000000 00000000 00000000
> (XEN)   [3f:20]  00000002 00000000 00000000
> (XEN)   [5f:40]  00000000 00000000 00000000
> (XEN)   [7f:60]  00000000 00000000 00000000
> (XEN)   [9f:80]  00000000 00000000 00000000
> (XEN)   [bf:a0]  00000000 00000000 00000000
> (XEN)   [df:c0]  00000000 00000000 00000000
> (XEN)   [ff:e0]  00000000 00000000 04000000

... IRR here.

> (XEN) Assertion '(sp == 0) || (peoi[sp-1].vector < vector)' failed at 
> irq.c:1340
> (XEN) ----[ Xen-4.12-unstable  x86_64  debug=y   Tainted:  C   ]----
> (XEN) CPU:    1
> (XEN) RIP:    e008:[<ffff82d08028737d>] do_IRQ+0x8df/0xacb
> (XEN) RFLAGS: 0000000000010002   CONTEXT: hypervisor
> (XEN) rax: ffff83086c67202c   rbx: 0000000000000180   rcx: 0000000000000000
> (XEN) rdx: ffff83086c68ffff   rsi: 000000000000000a   rdi: ffff83086c601e24
> (XEN) rbp: ffff83086c68fd98   rsp: ffff83086c68fd38   r8:  ffff83086c690000
> (XEN) r9:  0000000000000030   r10: 0000000004000000   r11: 0000000000000007
> (XEN) r12: 000000000000011f   r13: 00000000ffffffff   r14: ffff83086c601e00
> (XEN) r15: ffff82cfffffb100   cr0: 0000000080050033   cr4: 00000000003526e0

And then I'm having trouble guessing which register holds
"vector" here: r9 is the only one where I could sort of guess
it might be a vector, but then the assertion would not have
triggered. There's in particular no register with the low byte
being 0x21, nor is there any with it being 0xfa (to match the
bit that became set in IRR).

Could you please check or provide the disassembly?

Jan



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