[Xen-devel] [PATCH] Enable ERMS feature support for HVM and PV guests

["Yang, Wei Y" <wei.y.yang@xxxxxxxxx>]

This patch exposes ERMS feature to HVM and PV guests.

The REP MOVSB/STOSB instruction can enhance fast strings attempts to
move as much of the data with larger size load/stores as possible.

Signed-off-by: Yang, Wei <wei.y.yang@xxxxxxxxx>


---
 tools/libxc/xc_cpufeature.h      |    1 +
 tools/libxc/xc_cpuid_x86.c       |    6 ++++--
 xen/arch/x86/traps.c             |    3 ++-
 xen/include/asm-x86/cpufeature.h |    1 +
 4 files changed, 8 insertions(+), 3 deletions(-)

diff -r 782bc7b2661a tools/libxc/xc_cpufeature.h
--- a/tools/libxc/xc_cpufeature.h       Fri Jun 10 13:51:39 2011 +0100
+++ b/tools/libxc/xc_cpufeature.h       Mon Jun 13 20:55:37 2011 +0800
@@ -125,5 +125,6 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
 #define X86_FEATURE_FSGSBASE     0 /* {RD,WR}{FS,GS}BASE instructions */
 #define X86_FEATURE_SMEP         7 /* Supervisor Mode Execution Protection */
+#define X86_FEATURE_ERMS         9 /* Enhanced REP MOVSB/STOSB */
 
 #endif /* __LIBXC_CPUFEATURE_H */
diff -r 782bc7b2661a tools/libxc/xc_cpuid_x86.c
--- a/tools/libxc/xc_cpuid_x86.c        Fri Jun 10 13:51:39 2011 +0100
+++ b/tools/libxc/xc_cpuid_x86.c        Mon Jun 13 20:55:37 2011 +0800
@@ -354,7 +354,8 @@ static void xc_cpuid_hvm_policy(
 
     case 0x00000007: /* Intel-defined CPU features */
         if ( input[1] == 0 ) {
-            regs[1] &= bitmaskof(X86_FEATURE_SMEP);
+            regs[1] &= (bitmaskof(X86_FEATURE_SMEP) |
+                        bitmaskof(X86_FEATURE_ERMS));
         } else
             regs[1] = 0;
         regs[0] = regs[2] = regs[3] = 0;
@@ -477,7 +478,8 @@ static void xc_cpuid_pv_policy(
 
     case 7:
         if ( input[1] == 0 )
-            regs[1] &= bitmaskof(X86_FEATURE_FSGSBASE);
+            regs[1] &= (bitmaskof(X86_FEATURE_FSGSBASE) |
+                        bitmaskof(X86_FEATURE_ERMS));
         else
             regs[1] = 0;
         regs[0] = regs[2] = regs[3] = 0;
diff -r 782bc7b2661a xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c      Fri Jun 10 13:51:39 2011 +0100
+++ b/xen/arch/x86/traps.c      Mon Jun 13 20:55:37 2011 +0800
@@ -815,7 +815,8 @@ static void pv_cpuid(struct cpu_user_reg
         break;
     case 7:
         if ( regs->ecx == 0 )
-            b &= cpufeat_mask(X86_FEATURE_FSGSBASE);
+            b &= (cpufeat_mask(X86_FEATURE_FSGSBASE) |
+                  cpufeat_mask(X86_FEATURE_ERMS));
         else
             b = 0;
         a = c = d = 0;
diff -r 782bc7b2661a xen/include/asm-x86/cpufeature.h
--- a/xen/include/asm-x86/cpufeature.h  Fri Jun 10 13:51:39 2011 +0100
+++ b/xen/include/asm-x86/cpufeature.h  Mon Jun 13 20:55:37 2011 +0800
@@ -144,6 +144,7 @@
 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 7 */
 #define X86_FEATURE_FSGSBASE   (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
 #define X86_FEATURE_SMEP       (7*32+ 7) /* Supervisor Mode Execution 
Protection */
+#define X86_FEATURE_ERMS       (7*32+ 9) /* Enhanced REP MOVSB/STOSB */
 
 #define cpu_has(c, bit)                test_bit(bit, (c)->x86_capability)
 #define boot_cpu_has(bit)      test_bit(bit, boot_cpu_data.x86_capability)


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