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Re: [Xen-devel] How EPT translates an X86_32 guest physical address?

To: Superymk <superymkxen@xxxxxxxxxxx>, Xen-devel@xxxxxxxxxxxxxxxxxxx
Subject: Re: [Xen-devel] How EPT translates an X86_32 guest physical address?
From: Chu Rui <ruichu@xxxxxxxxx>
Date: Wed, 17 Nov 2010 17:20:48 +0800
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Maybe this figure depicts the process...

2010/11/17 Superymk <superymkxen@xxxxxxxxxxx>
Hi all,

Can some one please tell me how EPT translates an X86_32 guest physical address? I have read the Intel's manual, but it seems there is no discussion about this condition.

My concern is that, the guest CR3 pfn can be considered as being constituted by two 10 bits indexers for an X86_32 virtual machine. However, the EPT paging structures is similar with the page tables used on X86_64 platform. which has four 9 bits indexers in its address layout. In addition, each EPT entry is 64 bits long. Hence, a 4K page can hold at most 512 entries. So, if the guest CR3's pfn is 0xfffff (an X86_32 virtual machine) and I get a valid EPTP, how EPT will perform the translation?


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