This is an archived copy of the Xen.org mailing list, which we have preserved to ensure that existing links to archives are not broken. The live archive, which contains the latest emails, can be found at http://lists.xen.org/
Home Products Support Community News


[Xen-devel] How EPT translates an X86_32 guest physical address?

To: Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxx>
Subject: [Xen-devel] How EPT translates an X86_32 guest physical address?
From: Superymk <superymkxen@xxxxxxxxxxx>
Date: Wed, 17 Nov 2010 16:39:54 +0800
Delivery-date: Wed, 17 Nov 2010 00:40:58 -0800
Envelope-to: www-data@xxxxxxxxxxxxxxxxxxx
List-help: <mailto:xen-devel-request@lists.xensource.com?subject=help>
List-id: Xen developer discussion <xen-devel.lists.xensource.com>
List-post: <mailto:xen-devel@lists.xensource.com>
List-subscribe: <http://lists.xensource.com/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xensource.com?subject=subscribe>
List-unsubscribe: <http://lists.xensource.com/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xensource.com?subject=unsubscribe>
Sender: xen-devel-bounces@xxxxxxxxxxxxxxxxxxx
User-agent: Mozilla/5.0 (Windows; U; Windows NT 5.1; en-US; rv: Gecko/20101027 Thunderbird/3.1.6
Hi all,

Can some one please tell me how EPT translates an X86_32 guest physical address? I have read the Intel's manual, but it seems there is no discussion about this condition.

My concern is that, the guest CR3 pfn can be considered as being constituted by two 10 bits indexers for an X86_32 virtual machine. However, the EPT paging structures is similar with the page tables used on X86_64 platform. which has four 9 bits indexers in its address layout. In addition, each EPT entry is 64 bits long. Hence, a 4K page can hold at most 512 entries. So, if the guest CR3's pfn is 0xfffff (an X86_32 virtual machine) and I get a valid EPTP, how EPT will perform the translation?


Xen-devel mailing list