Re: [PATCH] xen/arm: gic-v3: Wait for redistributor RWP using the right bit

[Stefano Stabellini <sstabellini@xxxxxxxxxx>]

Oleksii, can we have a release ack for this fix?

On Fri, 15 May 2026, Luca Fancellu wrote:
> Hi Mykola,
> 
> > On 14 May 2026, at 10:08, Mykola Kvach <xakep.amatop@xxxxxxxxx> wrote:
> > 
> > From: Mykola Kvach <mykola_kvach@xxxxxxxx>
> > 
> > gicv3_do_wait_for_rwp() is used for both distributor and
> > redistributor writes. The CTLR register is at offset 0 for both,
> > but the RWP bit is not in the same position.
> > 
> > For GICD_CTLR, RWP is bit 31. For GICR_CTLR, bit 31 is UWP,
> > while RWP is bit 3. The redistributor wait path was therefore
> > polling UWP instead of RWP.
> > 
> > UWP covers upstream writes, including Generate SGI packets, and is
> > not a substitute for redistributor register write completion. The
> > existing redistributor callers need RWP semantics for redistributor
> > register writes such as GICR_ICENABLER0 and GICR_CTLR updates.
> > 
> > Add GICR_CTLR_RWP and pass the expected RWP bit to the shared
> > helper.
> > 
> > Fixes: bc183a0235e ("xen/arm: Add support for GIC v3")
> > Reported-by: Luca Fancellu <luca.fancellu@xxxxxxx>
> > Signed-off-by: Mykola Kvach <mykola_kvach@xxxxxxxx>
> > ---
> 
> This looks ok to me
> 
> Reviewed-by: Luca Fancellu <luca.fancellu@xxxxxxx>
> 
> Cheers,
> Luca
>