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Re: [PATCH] xen/arm: gic-v3: Wait for redistributor RWP using the right bit
- To: Mykola Kvach <xakep.amatop@xxxxxxxxx>
- From: Luca Fancellu <Luca.Fancellu@xxxxxxx>
- Date: Fri, 15 May 2026 11:13:16 +0000
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- Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Mykola Kvach <mykola_kvach@xxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Bertrand Marquis <Bertrand.Marquis@xxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
- Delivery-date: Fri, 15 May 2026 11:14:39 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
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- Thread-topic: [PATCH] xen/arm: gic-v3: Wait for redistributor RWP using the right bit
Hi Mykola,
> On 14 May 2026, at 10:08, Mykola Kvach <xakep.amatop@xxxxxxxxx> wrote:
>
> From: Mykola Kvach <mykola_kvach@xxxxxxxx>
>
> gicv3_do_wait_for_rwp() is used for both distributor and
> redistributor writes. The CTLR register is at offset 0 for both,
> but the RWP bit is not in the same position.
>
> For GICD_CTLR, RWP is bit 31. For GICR_CTLR, bit 31 is UWP,
> while RWP is bit 3. The redistributor wait path was therefore
> polling UWP instead of RWP.
>
> UWP covers upstream writes, including Generate SGI packets, and is
> not a substitute for redistributor register write completion. The
> existing redistributor callers need RWP semantics for redistributor
> register writes such as GICR_ICENABLER0 and GICR_CTLR updates.
>
> Add GICR_CTLR_RWP and pass the expected RWP bit to the shared
> helper.
>
> Fixes: bc183a0235e ("xen/arm: Add support for GIC v3")
> Reported-by: Luca Fancellu <luca.fancellu@xxxxxxx>
> Signed-off-by: Mykola Kvach <mykola_kvach@xxxxxxxx>
> ---
This looks ok to me
Reviewed-by: Luca Fancellu <luca.fancellu@xxxxxxx>
Cheers,
Luca
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