[PATCH 11/17] hvmloader: allocate MMCONFIG area in the MMIO hole

["Thierry Escande" <thierry.escande@xxxxxxxxxx>]

The actual MMCONFIG size depends on the number of PCI buses available
which should be covered by ECAM. Possible options are 64MB, 128MB and
256MB. As Xen is limited to the bus 0 currently, the lowest possible
setting is used (64MB), defined via PCI_MAX_MCFG_BUSES in
hvmloader/config.h. When multiple PCI buses support for Xen will be
implemented, PCI_MAX_MCFG_BUSES may be replaced by a calculation of the
number of buses according to PCI devices enumeration.

The MMCONFIG entry is inserted into bars array in the same manner like
for any other BARs. In this case, the devfn field will point to MCH PCI
device and bar_reg will contain PCIEXBAR register offset. It will be
assigned a slot in the MMIO hole later in a very same way like for plain
PCI BARs, with respect to its size and alignment. At this point, the
actual base address and size of the ECAM space are passed to Xen using
the HVMOP_set_ecam_space hypercall.

Signed-off-by: Alexey Gerasimenko <x1917x@xxxxxxxxx>
Signed-off-by: Thierry Escande <thierry.escande@xxxxxxxxxx>
---
 tools/firmware/hvmloader/config.h   |  4 +++
 tools/firmware/hvmloader/pci.c      | 55 +++++++++++++++++++++++++++++
 tools/firmware/hvmloader/pci_regs.h |  7 ++++
 3 files changed, 66 insertions(+)

diff --git a/tools/firmware/hvmloader/config.h 
b/tools/firmware/hvmloader/config.h
index baaed91c7f..aa3158bca5 100644
--- a/tools/firmware/hvmloader/config.h
+++ b/tools/firmware/hvmloader/config.h
@@ -55,6 +55,10 @@ extern uint32_t *cpu_to_apicid;
 #define PCI_ISA_DEVFN       0x08    /* dev 1, fn 0 */
 #define PCI_ISA_IRQ_MASK    0x0c20U /* ISA IRQs 5,10,11 are PCI connected */
 #define PCI_ICH9_LPC_DEVFN  0xf8    /* dev 31, fn 0 */
+#define PCI_MCH_DEVFN       0       /* bus 0, dev 0, func 0 */
+
+/* possible values are: 64, 128, 256 */
+#define PCI_MAX_MCFG_BUSES  64
 
 #define ACPI_TIS_HDR_ADDRESS 0xFED40F00UL
 
diff --git a/tools/firmware/hvmloader/pci.c b/tools/firmware/hvmloader/pci.c
index 6e6720adae..54c23ffdd8 100644
--- a/tools/firmware/hvmloader/pci.c
+++ b/tools/firmware/hvmloader/pci.c
@@ -413,6 +413,58 @@ void pci_setup(void)
         pci_devfn_decode_type[devfn] |= PCI_COMMAND_MASTER;
     }
 
+    /*
+     *  Calculate MMCONFIG area size and squeeze it into the bars array
+     *  for assigning a slot in the MMIO hole
+     */
+    if ( is_running_on_q35 )
+    {
+        /* disable PCIEXBAR decoding for now */
+        pci_writel(PCI_MCH_DEVFN, PCI_MCH_PCIEXBAR, 0);
+        pci_writel(PCI_MCH_DEVFN, PCI_MCH_PCIEXBAR + 4, 0);
+
+        switch ( PCI_MAX_MCFG_BUSES )
+        {
+        case 64:
+            bar_data = PCIEXBAR_64_BUSES | PCIEXBAR_ENABLE;
+            bar_sz = MB(64);
+            break;
+
+        case 128:
+            bar_data = PCIEXBAR_128_BUSES | PCIEXBAR_ENABLE;
+            bar_sz = MB(128);
+            break;
+
+        case 256:
+            bar_data = PCIEXBAR_256_BUSES | PCIEXBAR_ENABLE;
+            bar_sz = MB(256);
+            break;
+
+        default:
+            /* unsupported number of buses specified */
+            BUG();
+        }
+
+        addr_mask = ~(bar_sz - 1);
+
+        for ( i = 0; i < nr_bars; i++ )
+            if ( bars[i].bar_sz < bar_sz )
+                break;
+
+        if ( i != nr_bars )
+            memmove(&bars[i+1], &bars[i], (nr_bars-i) * sizeof(*bars));
+
+        bars[i].is_mem    = 1;
+        bars[i].devfn     = PCI_MCH_DEVFN;
+        bars[i].bar_reg   = PCI_MCH_PCIEXBAR;
+        bars[i].bar_sz    = bar_sz;
+        bars[i].addr_mask = addr_mask;
+        bars[i].bar_data  = bar_data;
+
+        mmio_total += bar_sz;
+        nr_bars++;
+    }
+
     if ( mmio_hole_size )
     {
         uint64_t max_ram_below_4g = GB(4) - mmio_hole_size;
@@ -592,6 +644,9 @@ void pci_setup(void)
             }
         }
 
+        if ( bar_reg == PCI_MCH_PCIEXBAR )
+            hvm_set_ecam_space(base, bar_sz);
+
         bar_data |= (uint32_t) (base & bars[i].addr_mask);
         bar_data_upper = (uint32_t)(base >> 32);
         base += bar_sz;
diff --git a/tools/firmware/hvmloader/pci_regs.h 
b/tools/firmware/hvmloader/pci_regs.h
index d217b8f1a4..86e04f8bbd 100644
--- a/tools/firmware/hvmloader/pci_regs.h
+++ b/tools/firmware/hvmloader/pci_regs.h
@@ -116,6 +116,13 @@
 #define PCI_CLASS_BRIDGE_OTHER           0x0680
 #define PCI_CLASS_BRIDGE_ISA             0x0601
 
+#define PCI_MCH_PCIEXBAR   0x60
+
+#define PCIEXBAR_64_BUSES  0x04
+#define PCIEXBAR_128_BUSES 0x02
+#define PCIEXBAR_256_BUSES 0x00
+#define PCIEXBAR_ENABLE    0x01
+
 #endif /* __HVMLOADER_PCI_REGS_H__ */
 
 /*
-- 
2.51.0



--
Thierry Escande | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech