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Re: [PATCH v3 2/7] x86/msi: Define extended destination ID masks and IO-APIC RTE fields
- To: Julian Vetter <julian.vetter@xxxxxxxxxx>
- From: Roger Pau Monné <roger.pau@xxxxxxxxxx>
- Date: Wed, 11 Mar 2026 11:15:18 +0100
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- Cc: xen-devel@xxxxxxxxxxxxxxxxxxxx, Jan Beulich <jbeulich@xxxxxxxx>, Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Anthony PERARD <anthony.perard@xxxxxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Juergen Gross <jgross@xxxxxxxx>, Julien Grall <julien@xxxxxxx>
- Delivery-date: Wed, 11 Mar 2026 10:15:28 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On Mon, Mar 09, 2026 at 12:31:02PM +0000, Julian Vetter wrote:
> x2APIC guests with more than 128 vCPUs need destination IDs beyond the
I think this needs to be re-worded:
"HVM guests with APIC IDs greater than 254 would be unable to use
those IDs as the target of external interrupts due to the lack of
emulated IOMMU. However there's an unofficial extension to the MSI
messages format that re-use some reserved bits to expand the
destination field from 8 to 15 bits."
Or similar.
> 8-bit range provided by the standard MSI address and IO-APIC RTE fields.
> The Intel spec allows bits 11:5 of the MSI address and bits 55:49 of the
> IO-APIC RTE to carry the high 7 bits of the destination ID when the
> platform advertises support, expanding the range to 15 bits total.
Hm, I'm really unsure the Intel spec allows for any of this. This is
something that has been done on the side, re-using bits marked as
reserved in the spec.
Thanks, Roger.
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