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Re: [PATCH v4 6/7] arm/mpu: Provide a constructor for pr_t type
- To: "Orzel, Michal" <Michal.Orzel@xxxxxxx>
- From: Luca Fancellu <Luca.Fancellu@xxxxxxx>
- Date: Tue, 6 May 2025 13:29:18 +0000
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- Cc: "xen-devel@xxxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxxx>, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Bertrand Marquis <Bertrand.Marquis@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
- Delivery-date: Tue, 06 May 2025 13:29:58 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
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- Thread-topic: [PATCH v4 6/7] arm/mpu: Provide a constructor for pr_t type
>> + switch ( attr_idx )
>> + {
>> + case MT_NORMAL_NC:
>> + /*
>> + * ARM ARM: Overlaying the shareability attribute (DDI
>> + * 0406C.b B3-1376 to 1377)
> It's a bit odd to provide here the manual for Armv7.
> Also, our general advice is to use the latest revision.
I’m thinking about restructuring in this way:
switch ( attr_idx )
{
/*
* ARM ARM: Shareable, Inner Shareable, and Outer Shareable Normal memory
* (DDI 0487L.a B2.10.1.1.1 Note section):
*
* Because all data accesses to Non-cacheable locations are data coherent
* to all observers, Non-cacheable locations are always treated as Outer
* Shareable
*
* ARM ARM: Device memory (DDI 0487L.a B2.10.2)
*
* All of these memory types have the following properties:
* [...]
* - Data accesses to memory locations are coherent for all observers in
* the system, and correspondingly are treated as being Outer Shareable
*/
case MT_NORMAL_NC:
/* Fall through */
case MT_DEVICE_nGnRnE:
/* Fall through */
case MT_DEVICE_nGnRE:
prbar.reg.sh = LPAE_SH_OUTER;
break;
default:
/* Xen mappings are SMP coherent */
prbar.reg.sh = LPAE_SH_INNER;
break;
}
what do you think? It will have the fall through comment and will also explain
the LPAE_SH_OUTER value set
for both normal memory nc and device memory.
Please let me know.
Cheers,
Luca
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