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RE: [PATCH 2/2] x86/vmx: Support for CPUs without model-specific LBR
- To: "andrew.cooper3@xxxxxxxxxx" <andrew.cooper3@xxxxxxxxxx>, Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: "Tian, Kevin" <kevin.tian@xxxxxxxxx>
- Date: Thu, 12 Jan 2023 01:39:05 +0000
- Accept-language: en-US
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- Cc: "andrew.cooper3@xxxxxxxxxx" <andrew.cooper3@xxxxxxxxxx>, "Beulich, Jan" <JBeulich@xxxxxxxx>, Pau Monné, Roger <roger.pau@xxxxxxxxxx>, Wei Liu <wl@xxxxxxx>, "Nakajima, Jun" <jun.nakajima@xxxxxxxxx>
- Delivery-date: Thu, 12 Jan 2023 01:39:15 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
- Thread-index: AQHZJCMek6T83CtFrkaQg0ivmixH/a6aBOsw
- Thread-topic: [PATCH 2/2] x86/vmx: Support for CPUs without model-specific LBR
> From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
> Sent: Monday, January 9, 2023 8:08 PM
>
> Ice Lake (server at least) has both Arch LBR and model-specific LBR. Sapphire
> Rapids does not have model-specific LBR at all. I.e. On SPR and later,
> model_specific_lbr will always be NULL, so we must make changes to avoid
> reliably hitting the domain_crash().
>
> The Arch LBR spec states that CPUs without model-specific LBR implement
> MSR_DBG_CTL.LBR by discarding writes and always returning 0.
>
> Do this for any CPU for which we lack model-specific LBR information.
>
> Adjust the now-stale comment, now that the Arch LBR spec has created a
> way to
> signal "no model specific LBR" to guests.
>
> Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Reviewed-by: Kevin Tian <kevin.tian@xxxxxxxxx>
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