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[PATCH 2/2] xen/arm: Enable CPU Errata 1165522 for Neoverse
- To: xen-devel@xxxxxxxxxxxxxxxxxxxx
- From: Bertrand Marquis <bertrand.marquis@xxxxxxx>
- Date: Tue, 18 Aug 2020 14:47:39 +0100
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- Cc: nd@xxxxxxx, Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>, Wei Chen <wei.chen@xxxxxxx>, Andre Przywara <andre.przywara@xxxxxxx>
- Delivery-date: Tue, 18 Aug 2020 13:48:47 +0000
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Enable CPU errata of Speculative AT on the Neoverse N1 processor
versions r0p0 to r2p0.
Also Fix Cortex A76 Errata string which had a wrong errata number.
Signed-off-by: Bertrand Marquis <bertrand.marquis@xxxxxxx>
---
xen/arch/arm/cpuerrata.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/cpuerrata.c b/xen/arch/arm/cpuerrata.c
index 0248893de0..6c09017515 100644
--- a/xen/arch/arm/cpuerrata.c
+++ b/xen/arch/arm/cpuerrata.c
@@ -476,9 +476,15 @@ static const struct arm_cpu_capabilities arm_errata[] = {
.matches = has_ssbd_mitigation,
},
#endif
+ {
+ /* Neoverse r0p0 - r2p0 */
+ .desc = "ARM erratum 1165522",
+ .capability = ARM64_WORKAROUND_AT_SPECULATE,
+ MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 2 << MIDR_VARIANT_SHIFT),
+ },
{
/* Cortex-A76 r0p0 - r2p0 */
- .desc = "ARM erratum 116522",
+ .desc = "ARM erratum 1165522",
.capability = ARM64_WORKAROUND_AT_SPECULATE,
MIDR_RANGE(MIDR_CORTEX_A76, 0, 2 << MIDR_VARIANT_SHIFT),
},
--
2.17.1
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