Re: [PATCH v3 2/2] x86/idle: prevent entering C6 with in service interrupts on Intel

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

On 21/05/2020 09:45, Roger Pau Monné wrote:
> On Wed, May 20, 2020 at 10:30:11PM +0100, Andrew Cooper wrote:
>> On 15/05/2020 14:58, Roger Pau Monne wrote:
>>> Apply a workaround for Intel errata BDX99, CLX30, SKX100, CFW125,
>>> BDF104, BDH85, BDM135, KWB131: "A Pending Fixed Interrupt May Be
>>> Dispatched Before an Interrupt of The Same Priority Completes".
>> HSM175 et al, so presumably a HSD, and HSE as well.
>>
>> On the broadwell side at least, BDD BDW in addition
> But those are a different errata AFAICT ('An APIC Timer Interrupt
> During Core C6 Entry May be Lost') and the workaround should also be
> different I think.

Hmm, so it is.

The issue in question here definitely does affect Haswell, because that
is where we first observed it.  There was also a report on xen-devel
against Haswell.

If the errata are missing, then I think Intel needs some more chasing to
work out the real extent of the problems.

> We should mark the lapic timer as not reliable on
> C6 or higher states in lapic_timer_reliable_states, so that it's
> disabled before entering sleep?

Probably should.

~Andrew