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Re: [PATCH v3 2/2] x86/idle: prevent entering C6 with in service interrupts on Intel

On Wed, May 20, 2020 at 10:30:11PM +0100, Andrew Cooper wrote:
> On 15/05/2020 14:58, Roger Pau Monne wrote:
> > Apply a workaround for Intel errata BDX99, CLX30, SKX100, CFW125,
> > BDF104, BDH85, BDM135, KWB131: "A Pending Fixed Interrupt May Be
> > Dispatched Before an Interrupt of The Same Priority Completes".
> HSM175 et al, so presumably a HSD, and HSE as well.
> On the broadwell side at least, BDD BDW in addition

But those are a different errata AFAICT ('An APIC Timer Interrupt
During Core C6 Entry May be Lost') and the workaround should also be
different I think. We should mark the lapic timer as not reliable on
C6 or higher states in lapic_timer_reliable_states, so that it's
disabled before entering sleep?

Thanks, Roger.



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