[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [PATCH v8 05/12] x86emul: support X{SUS,RES}LDTRK
On 08/05/2020 08:38, Jan Beulich wrote: > [CAUTION - EXTERNAL EMAIL] DO NOT reply, click links, or open attachments > unless you have verified the sender and know the content is safe. > > On 07.05.2020 22:13, Andrew Cooper wrote: >> On 05/05/2020 09:14, Jan Beulich wrote: >>> --- a/xen/tools/gen-cpuid.py >>> +++ b/xen/tools/gen-cpuid.py >>> @@ -284,6 +284,9 @@ def crunch_numbers(state): >>> # as dependent features simplifies Xen's logic, and prevents the >>> guest >>> # from seeing implausible configurations. >>> IBRSB: [STIBP, SSBD], >>> + >>> + # In principle the TSXLDTRK insns could also be considered >>> independent. >>> + RTM: [TSXLDTRK], >> Why the link? There is no relevant interaction AFAICT. > Do the insns make any sense without TSX? Anyway - hence the > comment, and if you're convinced the connection does not > need making, I'd be okay dropping it. I would assume though > that we'd better hide TSXLDTRK whenever we hide RTM, which > is most easily achieved by having a connection here. Actually - that is a very good point. I expect there will (or should) be an interaction with MSR_TSX_CTRL, as it has CPUID-hiding functionality. For now, could I ask you to not expose this to guests in this patch? For the emulator side of things alone I think this is ok (although looking over it a second time, we could really do with a comment in the code explaining that we're never in an RTM region, hence the nop behaviour). I'll follow up with Intel, and we can figure out the CPUID derivation details at a later point. If you're happy with this plan, then A-by to save a round trip. ~Andrew
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