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Re: [Xen-devel] [PATCH] x86/splitlock: CPUID and MSR details

On Thu, Feb 20, 2020 at 07:58:45PM +0000, Andrew Cooper wrote:
> A splitlock is an atomic operation which crosses a cache line boundary.  It
> serialises operations in the cache coherency fabric and comes with a
> multi-thousand cycle stall.
> Intel Tremont CPUs introduce MSR_CORE_CAPS to enumerate various core-specific
> features, and MSR_TEST_CTRL to adjust the behaviour in the case of a
> splitlock.
> Virtualising this for guests is distinctly tricky owing to the fact that
> MSR_TEST_CTRL has core rather than thread scope.  In the meantime however,
> prevent the MSR values leaking into guests.
> Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>

Reviewed-by: Wei Liu <wl@xxxxxxx>

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