[Xen-devel] [PATCH v6.5 25/26] x86/cpuid: Offer Indirect Branch Controls to guests

[Andrew Cooper <andrew.cooper3@xxxxxxxxxx>]

With all infrastructure in place, it is now safe to let guests see and use
these features.  Allow AMD's IBPB to be set even on Intel hardware, so the
toolstack can express "IBPB only" to guests.

This also requires updating the libxc logic to understand the e8b feature
leaf, which has the side effect of also offering CLZERO on applicable
hardware.

Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
---
v4:
 * Adjust for AMD changes
v5:
 * Support for IBRB-only
v6:
 * Fix AMD CPUID
---
 tools/libxc/xc_cpuid_x86.c                  | 4 +++-
 xen/arch/x86/cpuid.c                        | 8 ++++++++
 xen/include/public/arch-x86/cpufeatureset.h | 6 +++---
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
index 25b922e..9fa2f7c 100644
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -465,7 +465,9 @@ static void xc_cpuid_hvm_policy(xc_interface *xch,
 
     case 0x80000008:
         regs[0] &= 0x0000ffffu;
-        regs[1] = regs[3] = 0;
+        regs[1] = info->featureset[featureword_of(X86_FEATURE_CLZERO)];
+        /* regs[2] handled in the per-vendor logic. */
+        regs[3] = 0;
         break;
 
     case 0x00000002: /* Intel cache info (dumped by AMD policy) */
diff --git a/xen/arch/x86/cpuid.c b/xen/arch/x86/cpuid.c
index 2ef71d2..e1b8c7a 100644
--- a/xen/arch/x86/cpuid.c
+++ b/xen/arch/x86/cpuid.c
@@ -354,6 +354,14 @@ static void __init calculate_host_policy(void)
     recalculate_xstate(p);
     recalculate_misc(p);
 
+    /*
+     * AMD's IPBP is a subset of Intel's IBRS/IBPB.  For performance reasons,
+     * we may want to offer a guest only IBPB and not IBRS, so allow the AMD
+     * CPUID bit to be used whenever the hardware supports IBPB.
+     */
+    if ( p->feat.ibrsb )
+        p->extd.ibpb = true;
+
     if ( p->extd.svm )
     {
         /* Clamp to implemented features which require hardware support. */
diff --git a/xen/include/public/arch-x86/cpufeatureset.h 
b/xen/include/public/arch-x86/cpufeatureset.h
index e148755..aaeb149 100644
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -237,13 +237,13 @@ XEN_CPUFEATURE(EFRO,          7*32+10) /*   APERF/MPERF 
Read Only interface */
 
 /* AMD-defined CPU features, CPUID level 0x80000008.ebx, word 8 */
 XEN_CPUFEATURE(CLZERO,        8*32+ 0) /*A  CLZERO instruction */
-XEN_CPUFEATURE(IBPB,          8*32+12) /*   IBPB support only (no IBRS, used 
by AMD) */
+XEN_CPUFEATURE(IBPB,          8*32+12) /*A  IBPB support only (no IBRS, used 
by AMD) */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:0.edx, word 9 */
 XEN_CPUFEATURE(AVX512_4VNNIW, 9*32+ 2) /*A  AVX512 Neural Network Instructions 
*/
 XEN_CPUFEATURE(AVX512_4FMAPS, 9*32+ 3) /*A  AVX512 Multiply Accumulation 
Single Precision */
-XEN_CPUFEATURE(IBRSB,         9*32+26) /*   IBRS and IBPB support (used by 
Intel) */
-XEN_CPUFEATURE(STIBP,         9*32+27) /*   STIBP */
+XEN_CPUFEATURE(IBRSB,         9*32+26) /*A  IBRS and IBPB support (used by 
Intel) */
+XEN_CPUFEATURE(STIBP,         9*32+27) /*A  STIBP */
 
 #endif /* XEN_CPUFEATURE */
 
-- 
2.1.4


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