Re: [Xen-devel] [DOC RFC] Heterogeneous Multi Processing Support in Xen

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 07.12.16 at 19:29, <dario.faggioli@xxxxxxxxxx> wrote:
> ### x86
> 
> There is no HMP platform of relevance, for now, in x86 world. Therefore,
> only one class will exist, and all the CPUs will be set to belong to it.
> **TODO X86:** is this correct?

What about the original Xeon Phi (on a PCIe card)?

> ## Hypervisor
> 
> The hypervisor needs to know within which class each of the present CPUs
> falls. At boot (or, in general, CPU bringup) time, while identifying the CPU,
> a list of classes is constructed, and the mapping between each CPU and the
> class it is determined it should belong, established.
> 
> The list of classes is kept ordered from the more powerful to the less
> powerful.
> **TODO:** this has been [proposed by 
> George](https://lists.xenproject.org/archives/html/xen-devel/2016-09/msg02212.html).
> I like the idea, what do others think? If we agree on that, note that there
> has been no discussion on defining what "more powerful" means, neither on
> x86 (although, not really that interesting, for now, I'd say), nor on ARM.

Indeed I think there should be no assumption about the ability to
order things here: Even if for some initial set of hardware it may
be possible to clearly tell which one's more powerful and which
one's more weak, already the moment you extend this from
compute power to different ISA extensions you'll immediately end
up with the possibility of two CPUs have a distinct extra feature
compared to one another (say one a crypto extension and the
other a wider vector compute engine).

It may be possible to establish partial ordering though, but it's
not really clear to me what such ordering would be used for.

Jan


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