Re: [Xen-devel] [PATCH 2/2] AMD/VPMU: Keep reserved MSR bits untouched but allow the rest to be written

["Jan Beulich" <JBeulich@xxxxxxxx>]

>>> On 08.08.16 at 15:41, <boris.ostrovsky@xxxxxxxxxx> wrote:
> While AMD APM suggests that reserved MSR bits are not supposed to be
> touched, it is not clear how (or whether) HW enforces this for PMU
> registers. At least on some family 10h processors writes of these bits
> are apparently ignored: guests (such as Linux) assume that the bits
> are zero and write the MSRs with that assumption in mind even though
> the bits are set by the time OS/hypervisor starts runnning.

So how did these bits become non-zero then?

Independent of that I think the relaxation would better only be done
for those older CPUs.

Jan


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