[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [Xen-devel] Re: IOMMU faults
On 16/06 11:07, Tim Deegan wrote: > Hi Jean, > Reply below, > At 10:47 +0100 on 16 Jun (1308221277), Jean Guyader wrote: > > We have seed such behavior when we were testing GPU assignement especially > > the Intel GPU. The problem is that domain destruction in Xen is > > assynchronous > > and right now the pci device reset is done in dom0 with some help of the > > toolstack. > > > > In the Intel GPU case we need to make sure that the guest memory and the > > IOMMU > > are still in place while we perform to reset otherwise the device drift into > > an unstable state. > > > > There is probably other ways to do that in a cleaner way but we decided to > > move > > the pci reset code into Xen, so we are sure we perform the reset while the > > device > > is in a known state (functionning state). > > > > Attached is the patch we have in XenClient that move the pci reset into Xen. > > Thanks, Jean. This sounds like a good idea to me, though I'd like to > hear Wei and Allen's opinions. > > The patch is incomplete (missing the new pci_reset.[ch] files) but I get > the general idea. A few questions: Reattach the full patch. > > - Why the special handling for one graphics device on each domain? > (And if one, why not all?) No good reason really just a limitation of the patch, we can trivially get ride of the limitation. > - Why not reset when the target is dom0? It seems like it can do no > harm and should protect dom0 from assigning itself an active PCI > card. Reset could be quiet expensive (couple of seconds sometimes). We did that to avoid a double reset on domain reboot. I agree that we should remove that, or extend the IOMMU API so we can reassign from domU to domU without going through dom0. > > Of course, even with this patch, my original question still stands: > should Xen do something more assertive in the IOMMU fault handler? > What we really want to achive here is to stop DMA on this device. One way of doing it is to perform a proper PCI reset (FLR, secondary bus reset, ...) when that happens. Jean Attachment:
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