RE: [Xen-devel] TPR write optimization (even improves 2003 sp2)

["James Harper" <james.harper@xxxxxxxxxxxxxxxx>]

> On 07/01/2009 10:05, "James Harper" <james.harper@xxxxxxxxxxxxxxxx>
wrote:
> 
> >> Sometimes it triggers an interrupt to be delivered. So you'd need a
> > TPR
> >> threshold too to cause a VMEXIT sometimes. Or perhaps map the whole
> > APIC
> >> page and work it out yourself (possibly the Citrix drivers do this,
> > but
> >> I'm not really familiar with them).
> >
> > I can't see anything that would trigger an interrupt beyond
> > vlapic_write(). Is it just the act of invoking a VMEXIT that
triggers
> > the interrupt delivery?
> 
> Yes. See vmx_intr_assist().

I can see the vmx_intr_assist function, but I can't find what calls it.

Is vmx code for both amd and intel? Or is it vmx=intel and svm=amd? I've
never got my head around those terms...

> > From memory, there is a register somewhere that says what the
highest
> > interrupt level that is currently blocked is... I'll look at that.
This
> > doesn't actually sound that hard...
> 
> An interrupt is delivered if:
>   highest_prio(IRR) > max(highest_prio(ISR), TPR).
> 
> Where highest_prio() is based on a backwards bitmap scan.
> 
> If you go down the route of setting a TPR threshold for vmexit, that
would
> be (hp = highest_prio):
>   TPR_thresh = ((hp(IRR) > hp(ISR)) && (hp(IRR) < TPR)) ? hp(IRR) : 0
> 
> Where VMEXIT occurs if TPR is updated to a value less than the
threshold.
> 

Hmmm... if I do things in the right order I should be able to avoid
races.

James

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