[XenPPC] Re: Add Function to completely flush the I-Cache for a processor

[Hollis Blanchard <hollisb@xxxxxxxxxx>]

On Mon, 2006-10-02 at 22:02 +0000, Xen patchbot-xenppc-unstable wrote:
> 
> +void cpu_flush_icache(void)
> +{
> +    union hid1 hid1;
> +    ulong flags;
> +    ulong ra;
>
> +    local_irq_save(flags);
> +
> +    /* uses special processor mode that forces a real address match */
> +    hid1.word = mfhid1();
> +    hid1.bits.en_icbi = 1;
> +    mthid1(hid1.word);

icbi uses effective addresses, not real addresses. The docs say that bit
is "Enable forced Instruction Cache Block Invalidate (icbi) match mode,"
which I don't understand.

Are you saying that bit makes the invalidate work on real addresses
rather than effective? Why would we want that? Doesn't this loop work
just fine with effective addresses?

> +    for (ra = 0; ra < cpu_caches.isize; ra += cpu_caches.iline_size)
> +        icbi(ra);
> +
> +    sync();
> +
> +    hid1.bits.en_icbi = 0;
> +    mthid1(hid1.word);
> +
> +    local_irq_save(flags);
> +} 

^^^ local_irq_restore

-- 
Hollis Blanchard
IBM Linux Technology Center


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