Hi,
Because I was a business trip yesterday, I was behind with reading an
email of all of you.
I'm working on FPSWA support now.
I inserted FPSWA codes in ITC with the below patch, and I passed tests
of a floating point by LTP. Please give me comment.
diff -r 7ed6c203efe9 xen/arch/ia64/xen/ivt.S
--- a/xen/arch/ia64/xen/ivt.S Wed Apr 19 10:39:15 2006 -0600
+++ b/xen/arch/ia64/xen/ivt.S Thu Apr 20 17:17:23 2006 +0900
@@ -465,12 +465,21 @@ late_alt_itlb_miss:
or r19=r19,r18 // set bit 4 (uncached) if the access was to
region 6
(p8) br.cond.spnt page_fault
#ifdef XEN
- FORCE_CRASH
+ ;;
+ // Test for Xen address, if not handle via page_fault
+ // note that 0xf000 (cached) addresses should be OK.
+ extr.u r22=r16,59,5;;
+ cmp.ne p8,p0=0x1e,r22
+(p8) br.cond.spnt 1f
#endif
;;
itc.i r19 // insert the TLB entry
mov pr=r31,-1
rfi
+#ifdef XEN
+1:
+ FORCE_CRASH
+#endif
END(alt_itlb_miss)
.org ia64_ivt+0x1000
Best regars,
Kan
Alex Williamson wrote:
>On Wed, 2006-04-19 at 11:50 +0900, Isaku Yamahata wrote:
>> On Wed, Apr 19, 2006 at 09:05:49AM +0800, Tian, Kevin wrote:
>> >
>> > So the logic to support identity mapped ITC insertion should be
>> > added to itlb_miss handler, however the interesting thing is why
>> > you encounter it in alt_itlb_miss handler. As above debug output,
>> > the rr7 is also configured with vhpt table enabled...
>>
>> PSR.dt = 0 or PSR.ic = 0?
>> If so, the assumption that alt_itlb_miss handler dosn't occur is incorrect.
>
> I traced through one more time. Looks like I missed the initial
>entry into the IVT. I'm taking an itlb_miss, then branching to the
>alt_itlb_miss in VHPT_CCHAIN_LOOKUP. PSR.dt = PSR.ic = 1. Hopefully
>that clarifies how we're getting into alt_itlb_miss in a vhpt covered
>region. AFAICT, the logic exists in alt_itlb_miss to fill the itc for
>this, but it's disable by the FORCE_CRASH. Thanks,
>
> Alex
>
>--
>Alex Williamson HP Linux & Open Source Lab
>
>
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