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Re: [Xen-ia64-devel] vIOSAPIC and IRQs delivery

To: "Dong, Eddie" <eddie.dong@xxxxxxxxx>, "Tian, Kevin" <kevin.tian@xxxxxxxxx>, "Magenheimer, Dan \(HP Labs Fort Collins\)" <dan.magenheimer@xxxxxx>, <xen-ia64-devel@xxxxxxxxxxxxxxxxxxx>
Subject: Re: [Xen-ia64-devel] vIOSAPIC and IRQs delivery
From: Tristan Gingold <Tristan.Gingold@xxxxxxxx>
Date: Fri, 10 Mar 2006 12:02:35 +0100
Delivery-date: Fri, 10 Mar 2006 10:59:46 +0000
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Le Jeudi 09 Mars 2006 23:55, Dong, Eddie a écrit :
> Let me put small comments before US guys call it a day.
>
> Tian, Kevin wrote:
> >> From: Magenheimer, Dan (HP Labs Fort Collins)
> >> Sent: 2006年3月10日 2:45
> >>
> >> 1) Interrupts may happen at a rate of tens of thousands
> >>   per second.  Just like all high frequency CPU operations
> >>   are coded with "fast paths" (hyperprivops and hyperreflection),
> >>   I think interrupt reflection (some call it injection)
> >>   needs to be implemented with a fast path.  Unlike the
> >>   CPU ops, there is currently no fast path for external
> >>   interrupt reflection, though many of the CPU ops that
> >>   a guest performs (e.g. ivr, eoi, tpr) DO have fast paths.
> >
> > Yes, interrupt should be implemented with high performance.
>
> Yes, this is the benefit of event channel based solution. With more
> frequent the IRQ happens, event channel has more obvious performance gain.
> As TPR/IVR is done in Xen already in event channel based solution, then
> no/less ring crossing after the guest services IRQ.
I don't think ring crossing costs much.  This is not x86.
Maybe I am wrong about this.

> Reflecting a IRQ to guest on event channel based solution is just setting a
> bit in shared memory and they are batched (the guest will not immediately
> get scheduled), similar with vIRR setting.
>
> Meanwhile, the guest will batch extract these information from the shared
> memory and call do_IRQ one by one. The mechanism is almost same with
> linux/IA64 IRQ handling (read IVR and batch handle it).

You said performance was secondary.

If we talk about performance, Xen/ia64 almost has fast reflexion.  I think you 
need to do this with event channel to reach interrupt injection with fast 
reflexion performance.
As a consequence, you will have to write some amount of event channel code in 
asm.  And you will diverge from x86.  If event channel code change, the 
maintainance will be high.  The same cannot happen with interrupt injection, 
because it is done like hardware which doesn't change and because it is 
Xen/ia64 private, so we control it.

But maintainance of event channel was a primary pros for you.

Tristan.

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