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Re: [Xen-devel] Vitrual TLBs

Liang Yang wrote:
AMD will provide support for nested paging that caches address translations
to reduce memory accesses in its latest quad-core CPUs. As the hypervisor
can get pretty bogged down managing all of this and the processor is
constantly switching from guest OS mode to hypervisor mode and back, Nesting page tables and caching memory addresses are ways of freeing things up as it
cuts down on memory access time.

So Xen may not need such kind of virtual TLB anymore.

If by virtual TLB you are actually referring to shadow paging (and I would argue that they are very different concepts), then sorry, I misunderstood the initial question.

Yes, Xen supports shadow paging. Both Intel and AMD are planning on supporting hardware shadow paging too in future processors. I think it remains to be see if the hardware shadow paging is flexible enough to totally replace software shadow paging.

Regards,

Anthony Liguori

Liang

----- Original Message -----
From: "Anthony Liguori" <aliguori@xxxxxxxxxx>
To: "Sameer Ahuja" <sameer.ahuja@xxxxxxxxxxx>
Cc: "Tim Deegan" <Tim.Deegan@xxxxxxxxxxxxx>; <sameer.ahuja81@xxxxxxxxx>;
<xen-devel@xxxxxxxxxxxxxxxxxxx>
Sent: Monday, November 20, 2006 9:53 AM
Subject: Re: [Xen-devel] Vitrual TLBs


Sameer Ahuja wrote:
Hi,

Does XEN have the concept of virtual TLBs?


Not really.

Regards,

Anthony Liguori

Regards,
Sameer

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