# HG changeset patch
# User djm@xxxxxxxxxxxxxxx
# Node ID 816b9b3ced2f8b82d20c505b05f6519c8e23b550
# Parent a83ac0806d6b900eafac6e6942352f88fe89d449
Fix ar.unat handling for fast paths
diff -r a83ac0806d6b -r 816b9b3ced2f xen/arch/ia64/domain.c
--- a/xen/arch/ia64/domain.c Fri Jul 15 13:39:50 2005
+++ b/xen/arch/ia64/domain.c Fri Jul 15 22:27:06 2005
@@ -311,9 +311,10 @@
init_all_rr(v);
// this should be in userspace
- regs->r28 = dom_fw_setup(v->domain,"nomca nosmp xencons=ttyS
console=ttyS0",256L); //FIXME
+ regs->r28 = dom_fw_setup(v->domain,"nomca nosmp xencons=tty0
console=tty0",256L); //FIXME
v->vcpu_info->arch.banknum = 1;
v->vcpu_info->arch.metaphysical_mode = 1;
+ v->arch.domain_itm_last = -1L;
v->domain->shared_info->arch = c->shared;
return 0;
diff -r a83ac0806d6b -r 816b9b3ced2f xen/arch/ia64/hyperprivop.S
--- a/xen/arch/ia64/hyperprivop.S Fri Jul 15 13:39:50 2005
+++ b/xen/arch/ia64/hyperprivop.S Fri Jul 15 22:27:06 2005
@@ -21,6 +21,8 @@
#define FAST_TICK
#define FAST_BREAK
#define FAST_ACCESS_REFLECT
+#define FAST_RFI
+#define FAST_SSM_I
#undef RFI_TO_INTERRUPT // not working yet
#endif
@@ -183,6 +185,9 @@
// r19 == vpsr.ic (low 32 bits) | vpsr.i (high 32 bits)
// r31 == pr
ENTRY(hyper_ssm_i)
+#ifndef FAST_SSM_I
+ br.spnt.few dispatch_break_fault ;;
+#endif
// give up for now if: ipsr.be==1, ipsr.pp==1
mov r30=cr.ipsr;;
mov r29=cr.iip;;
@@ -259,7 +264,8 @@
adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18;
adds r3=(XSI_BANK1_OFS+8)-XSI_PSR_IC_OFS,r18;;
bsw.1;;
- // FIXME: need to handle ar.unat!
+ // FIXME?: ar.unat is not really handled correctly,
+ // but may not matter if the OS is NaT-clean
.mem.offset 0,0; st8.spill [r2]=r16,16;
.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
.mem.offset 0,0; st8.spill [r2]=r18,16;
@@ -424,11 +430,10 @@
add r24=r24,r23;;
mov cr.iip=r24;;
// OK, now all set to go except for switch to virtual bank0
- mov r30=r2; mov r29=r3;;
+ mov r30=r2; mov r29=r3;; mov r28=ar.unat;
adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18;
adds r3=(XSI_BANK1_OFS+8)-XSI_PSR_IC_OFS,r18;;
bsw.1;;
- // FIXME: need to handle ar.unat!
.mem.offset 0,0; st8.spill [r2]=r16,16;
.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
.mem.offset 0,0; st8.spill [r2]=r18,16;
@@ -447,7 +452,11 @@
.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
movl r31=XSI_IPSR;;
bsw.0 ;;
- mov r2=r30; mov r3=r29;;
+ // bank0 regs have no NaT bit, so ensure they are NaT clean
+ mov r16=r0; mov r17=r0; mov r19=r0;
+ mov r21=r0; mov r22=r0; mov r23=r0;
+ mov r24=r0; mov r25=r0; mov r26=r0; mov r27=r0;
+ mov r2=r30; mov r3=r29; mov ar.unat=r28;
adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
st4 [r20]=r0 ;;
fast_tick_reflect_done:
@@ -566,11 +575,10 @@
add r20=r20,r23;;
mov cr.iip=r20;;
// OK, now all set to go except for switch to virtual bank0
- mov r30=r2; mov r29=r3;;
+ mov r30=r2; mov r29=r3;; mov r28=ar.unat;
adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18;
adds r3=(XSI_BANK1_OFS+8)-XSI_PSR_IC_OFS,r18;;
bsw.1;;
- // FIXME: need to handle ar.unat!
.mem.offset 0,0; st8.spill [r2]=r16,16;
.mem.offset 8,0; st8.spill [r3]=r17,16 ;;
.mem.offset 0,0; st8.spill [r2]=r18,16;
@@ -589,7 +597,11 @@
.mem.offset 8,0; st8.spill [r3]=r31,16 ;;
movl r31=XSI_IPSR;;
bsw.0 ;;
- mov r2=r30; mov r3=r29;;
+ // bank0 regs have no NaT bit, so ensure they are NaT clean
+ mov r16=r0; mov r17=r0; mov r19=r0;
+ mov r21=r0; mov r22=r0; mov r23=r0;
+ mov r24=r0; mov r25=r0; mov r26=r0; mov r27=r0;
+ mov r2=r30; mov r3=r29; mov ar.unat=r28;
adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
st4 [r20]=r0 ;;
mov pr=r31,-1 ;;
@@ -637,6 +649,9 @@
// ensure that, if giving up, registers at entry to fast_hyperprivop unchanged
ENTRY(hyper_rfi)
+#ifndef FAST_RFI
+ br.spnt.few dispatch_break_fault ;;
+#endif
// if no interrupts pending, proceed
mov r30=r0
cmp.eq p7,p0=r20,r0
@@ -736,7 +751,8 @@
adds r2=XSI_BANK1_OFS-XSI_PSR_IC_OFS,r18;
adds r3=(XSI_BANK1_OFS+8)-XSI_PSR_IC_OFS,r18;;
bsw.1;;
- // FIXME: need to handle ar.unat!
+ // FIXME?: ar.unat is not really handled correctly,
+ // but may not matter if the OS is NaT-clean
.mem.offset 0,0; ld8.fill r16=[r2],16 ;
.mem.offset 8,0; ld8.fill r17=[r3],16 ;;
.mem.offset 0,0; ld8.fill r18=[r2],16 ;
diff -r a83ac0806d6b -r 816b9b3ced2f xen/arch/ia64/xenmisc.c
--- a/xen/arch/ia64/xenmisc.c Fri Jul 15 13:39:50 2005
+++ b/xen/arch/ia64/xenmisc.c Fri Jul 15 22:27:06 2005
@@ -291,8 +291,8 @@
static long cnt[16] = { 50,50,50,50,50,50,50,50,50,50,50,50,50,50,50,50};
static int i = 100;
int id = ((struct vcpu *)current)->domain->domain_id & 0xf;
-if (!cnt[id]--) { printk("%x",id); cnt[id] = 500; }
-if (!i--) { printk("+",id); cnt[id] = 1000; }
+if (!cnt[id]--) { printk("%x",id); cnt[id] = 50000; }
+if (!i--) { printk("+",id); i = 100000; }
}
clear_bit(_VCPUF_running, &prev->vcpu_flags);
//if (!is_idle_task(next->domain) )
diff -r a83ac0806d6b -r 816b9b3ced2f xen/common/xmalloc.c
--- a/xen/common/xmalloc.c Fri Jul 15 13:39:50 2005
+++ b/xen/common/xmalloc.c Fri Jul 15 22:27:06 2005
@@ -111,7 +111,9 @@
unsigned long flags;
/* We currently always return cacheline aligned. */
+#ifndef __ia64__
BUG_ON(align > SMP_CACHE_BYTES);
+#endif
/* Add room for header, pad to align next header. */
size += sizeof(struct xmalloc_hdr);
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