RE: [Xen-ia64-devel] vIOSAPIC and IRQs delivery

["Tian, Kevin" <kevin.tian@xxxxxxxxx>]

>From: Tristan Gingold
>Sent: 2006年3月9日 16:17
>
>> Expensive? Yes.
>>
>> There are only 255 irqs - minus some that the base kernel steals
>> for cmc, mca, timer, perfmon, etc.  So any large system with a
>> few hundred i/o cards _must_ share irqs.  There aren't enough
>> for one each.
>I don't agree.  You can have interrupt domains.  See "Intel Itanium Processor
>Family Interrupt Architecture Guide".
>
>Tristan.

OK, interrupt domains are only one option provided together with other 
two: share level-triggered irq line, and share vector number with multiple 
RTEs. Term "You" here refers to vendors, instead of us software developers. 
Vendors can support interrupt domains by providing multiple IOSAPICs, or 
they may implement by sharing level-triggered irq line physically. From 
VMM point of view, it shouldn't assume interrupt domains as the only 
option, and has to cover all cases.

To me, it's also likely to imagine a mixed style: multiple IOSAPICs provided 
by the platform with total irq lines less than number of interrupt sources. In 
that case, people may partition interrupt domains, but finally still with irq 
line
sharing even within local domain if it's electronically wired together. :-)

Thanks,
Kevin

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