RE: [Xen-ia64-devel] vIOSAPIC and IRQs delivery

["Magenheimer, Dan (HP Labs Fort Collins)" <dan.magenheimer@xxxxxx>]

Hi Tristan --

Do you have any more design information?  I'm not very
familiar with the x86 implementation but is it your intent
for it to be (nearly) identical?  What would be different?

Would all hardware I/O interrupts require queueing by
Xen in an event channel?  This seems like it could be
a potential high overhead performance issue.

Perhaps a design document (or at least a few paragraphs)
would be useful for the developers on the list.

Thanks,
Dan

> -----Original Message-----
> From: xen-ia64-devel-bounces@xxxxxxxxxxxxxxxxxxx 
> [mailto:xen-ia64-devel-bounces@xxxxxxxxxxxxxxxxxxx] On Behalf 
> Of Tristan Gingold
> Sent: Friday, March 03, 2006 8:35 AM
> To: xen-ia64-devel@xxxxxxxxxxxxxxxxxxx
> Subject: [Xen-ia64-devel] vIOSAPIC and IRQs delivery
> 
> Hi,
> 
> last weeks I have been delivering vIOSAPIC patch.  I got many 
> comments from 
> Intel.
> 
> Intel would like to take advantage of vIOSAPIC to speed up 
> convergence with 
> x86 code.  That means using safe callback, delivering 
> interrupts through the 
> event channel and being ready for domain drivers.
> 
> I think this convergence is a good goal but this is also a 
> big change.  Of 
> course this can be done incremently and I think vIOSAPIC is a 
> first step.
> 
> However, I don't remember general agreement about that during 
> the Xen summit 
> (I am sure we spoke about vIOSAPIC but not beyond).
> 
> Before working on such changes, I'd like to get any comments 
> and I'd like to 
> reach a consensus.
> 
> Tristan.
> 
> _______________________________________________
> Xen-ia64-devel mailing list
> Xen-ia64-devel@xxxxxxxxxxxxxxxxxxx
> http://lists.xensource.com/xen-ia64-devel
> 

_______________________________________________
Xen-ia64-devel mailing list
Xen-ia64-devel@xxxxxxxxxxxxxxxxxxx
http://lists.xensource.com/xen-ia64-devel