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xen-ia64-devel
RE: [Xen-ia64-devel] [PATCH] translate_domain_pte must handle ED bit
> On Mon, Feb 20, 2006 at 10:54:41PM +0800, Tian, Kevin wrote:
> > >From: Isaku Yamahata
> > >Sent: 2006年2月20日 16:32
> > >
> > >translate_domain_pte() must handle ED bit explicitly.
> > >This case can occur because of vcpu_itc_d().
> > >
> > >--
> > >Yamahata
> >
> > Seems a bug, however do you know why it only jumps out now?
> Seems PAGE_ED is likely on in lookup_domain_mpa...
>
> Perhaps vcpu->arch.dtlb cache hit in vcpu_translate() is very rare
> because of tlb cache and VHPT.
> To hit this bug it would be necessary to run a huge amount of
> guest domains competing tlb cache and VHPT entries.
> It seems that no one does.
I know that definitely the vcpu->arch.dtlb cache gets used,
at least when I run my compile-Linux-many-times-in-both-
domain0-and-domU test. It is rare though. You may want to
add a printk to see for yourself.
> > BTW, bit[53-63] are ignored bits per 4.1.1.5 of SDM2, and
> then you can just ignore them instead of BUG there. ;-)
>
> Hmm, the current code seems to assume just simply that bit[53-63] and
> ED bit[52] can be used for address machine page frame number.
> Some clean up might be needed.
FYI, I was hoping that some day we might be able to use some ignored
bits to indicate the contiguous block size that the page belongs
to. E.g. even if the page is 16K, if it is part of an aligned
contiguous block of 64K where phys==machine, the larger block size
could be put into the TLB. This obviously was never implemented
(and could cause extra flushing overhead if the p2m mapping changed
for any of the "sub pages" so may not even be advantageous).
Dan
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