Anthony,
As far as I know, existing processor implementations (i.e. Itanium 1
& Itanium 2) only implement lazy mode. Is this no longer true...?
Matt
On Tue, Sep 13, 2005 at 05:07:36PM +0800, Xu, Anthony wrote:
> Dan,
>
> In current implementation, Guest stack register of current guest
> function can be saved in hypervisor backing store or/and guest backing
> store, if some saved in guest backing store, set/get-rse-reg will
> directly access guest backing store, at this time, tlb miss may happen.
> But tlb miss handler only search guest vhpt not guest page table, that
> means it is possible hypervisor can't handle this tlb miss and inject
> tlb miss to guest kernel, at this situation, I think hypervisor can't
> inject tlb miss to guest kernel.
> One explicit solution is in ivt.S set rse to lazy mode before do 'cover'
> to make sure guest stack register of current guest function are all
> saved in hypervisor backing store. Yes this solution will penalize
> performance, but just a little, because there are only about ten
> assembly instructions between 'cover' and 'mov ar.rse=0' in current
> implementation.
> What's your opinion?
>
> Thanks
> Anthony.
>
> _______________________________________________
> Xen-ia64-devel mailing list
> Xen-ia64-devel@xxxxxxxxxxxxxxxxxxx
> http://lists.xensource.com/xen-ia64-devel
_______________________________________________
Xen-ia64-devel mailing list
Xen-ia64-devel@xxxxxxxxxxxxxxxxxxx
http://lists.xensource.com/xen-ia64-devel
|
Home