Re: [Xen-ia64-devel] RE: rid virtualization

[Matt Chapman <matthewc@xxxxxxxxxxxxxxx>]

On Mon, Sep 05, 2005 at 07:59:59AM -0700, Magenheimer, Dan (HP Labs Fort 
Collins) wrote:
> > > This seems very counter-intuitive.  What is the hardware hash
> > > algorithm? Surely there is a way to "mangle" rid bits to match this
> > > algorithm and use more of the VHPT?
> 
> > The hardware hash algrorithm is not public and is 
> > implementation specific,
> 
> The algorithm for Itanium2 seems to be here (see #8):
> http://www.gelato.unsw.edu.au/IA64wiki/ItaniumInternals
> If this is correct, the current mangling algorithm seems
> like it should work.  I wonder if the virtual addresses
> used by Linux are counteracting it?

The same algorithm (VPN xor RID) is used by both Itanium 1
and Itanium 2, and I imagine Montecito will follow suit,
though I don't have access to a Montecito box yet.  I think
it's fair enough to tune the implementation assuming this.

> I don't have access to HP-UX source but will see if I can
> find out.  Also, there has been a LVHPT implementation on
> Linux... perhaps the UNSW folks have some insight into this?

We use a similar mangling algorithm on Linux, but switching the
bottom two bytes.  IMHO this is better than switching first and
third, because the third byte is not really used for hashing
unless your VHPT is very big.  Do you know which HP-UX does?
(1/3 or 1/2?)

#define redistribute_rid(rid)   (((rid) & ~0xffff) | (((rid) << 8) & 0xff00) | 
(((rid) >> 8) & 0xff))

There is significant improvement over not doing the mangling,
though I don't know how far away it is from optimal.

Matt

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