On Wed, 2011-06-01 at 10:39 +0100, Ian Campbell wrote:
> # HG changeset patch
> # User Ian Campbell <ian.campbell@xxxxxxxxxx>
> # Date 1306916791 -3600
> # Node ID 062bc0a35d9933cc64c11f861609559e11994778
> # Parent 253a38db096bdc72b4e266ed103643210a739d93
> hvmloader: enable PCI_COMMAND_IO on primary VGA device
>
> There is an implicit assumption in the PCI spec that the primary VGA
> device (e.g. something with class==VGA) will have I/O enabled in order
> to make the standard VGA I/O registers (e.g. at 0x3xx) available, even
> though the device has no explicit I/O BARS.
>
> The qemu device model for the Cirrus VGA card does not actually
> enforce this but SeaBIOS looks for a VGA device with I/O enabled
> before running the VGA ROM. Coreboot has similar behaviour and I
> verified on a physical Cirrus GD 5446 that the BIOS had enable I/O
> cycles.
>
> The thread at http://www.seabios.org/pipermail/seabios/2011-May/001804.html
> contains more info.
>
> Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
Actually, this doesn't do quite what I expected. The value of
virtual_vga can change multiple times if an PT device is found before
one of the emulated devices. Since we want this devfn to match the
device we have chosen as primary we should always update both together.
The following does that. This change conflicts with 3/15 so I will
repost that too shortly.
8<-------------------------------------------------
# HG changeset patch
# User Ian Campbell <ian.campbell@xxxxxxxxxx>
# Date 1306922623 -3600
# Node ID e28514b40c909f882e7075d05e614a8814786ad2
# Parent 253a38db096bdc72b4e266ed103643210a739d93
hvmloader: enable PCI_COMMAND_IO on primary VGA device
There is an implicit assumption in the PCI spec that the primary VGA
device (e.g. something with class==VGA) will have I/O enabled in order
to make the standard VGA I/O registers (e.g. at 0x3xx) available, even
though the device has no explicit I/O BARS.
The qemu device model for the Cirrus VGA card does not actually
enforce this but SeaBIOS looks for a VGA device with I/O enabled
before running the VGA ROM. Coreboot has similar behaviour and I
verified on a physical Cirrus GD 5446 that the BIOS had enable I/O
cycles.
The thread at http://www.seabios.org/pipermail/seabios/2011-May/001804.html
contains more info.
Signed-off-by: Ian Campbell <ian.campbell@xxxxxxxxxx>
diff -r 253a38db096b -r e28514b40c90 tools/firmware/hvmloader/rombios.c
--- a/tools/firmware/hvmloader/rombios.c Wed Jun 01 09:17:55 2011 +0100
+++ b/tools/firmware/hvmloader/rombios.c Wed Jun 01 11:03:43 2011 +0100
@@ -102,6 +102,7 @@ static void rombios_apic_setup(void)
static void rombios_pci_setup(void)
{
uint32_t base, devfn, bar_reg, bar_data, bar_sz, cmd, mmio_total = 0;
+ uint32_t vga_devfn = 256;
uint16_t class, vendor_id, device_id;
unsigned int bar, pin, link, isa_irq;
@@ -146,12 +147,22 @@ static void rombios_pci_setup(void)
{
case 0x0300:
/* If emulated VGA is found, preserve it as primary VGA. */
+ if ( virtual_vga == VGA_none )
if ( (vendor_id == 0x1234) && (device_id == 0x1111) )
+ {
+ vga_devfn = devfn;
virtual_vga = VGA_std;
+ }
else if ( (vendor_id == 0x1013) && (device_id == 0xb8) )
+ {
+ vga_devfn = devfn;
virtual_vga = VGA_cirrus;
+ }
else if ( virtual_vga == VGA_none )
+ {
+ vga_devfn = devfn;
virtual_vga = VGA_pt;
+ }
break;
case 0x0680:
/* PIIX4 ACPI PM. Special device with special PCI config space. */
@@ -307,6 +318,18 @@ static void rombios_pci_setup(void)
cmd |= PCI_COMMAND_IO;
pci_writew(devfn, PCI_COMMAND, cmd);
}
+
+ if ( vga_devfn != 256 )
+ {
+ /*
+ * VGA registers live in I/O space so ensure that primary VGA
+ * has IO enabled, even if there is no I/O BAR on that
+ * particular device.
+ */
+ cmd = pci_readw(vga_devfn, PCI_COMMAND);
+ cmd |= PCI_COMMAND_IO;
+ pci_writew(vga_devfn, PCI_COMMAND, cmd);
+ }
}
/*
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