Re: [Xen-devel] How EPT translates an X86_32 guest physical address?

[Superymk <superymkxen@xxxxxxxxxxx>]

Thanks a lot, George. Also thanks for Chu's material.

On 11/17/2010 6:32 PM, George Dunlap wrote:
> The exact implementation of 32-bit mode on a 64-bit capable processor 
> is something only the engineers at Intel know; but logically yes, 
> whatever it does is equivalent to first zero-extending the 32-bit value.
> You can see the software implementation in 
> xen/arch/x86/mm/hap/p2m-ept.c:ept_get_entry().  That function is 
> passed an unsigned long, which in 64-bit mode is 64 bits, so at that 
> point any hardware address would have been zero-extended.
>  -George
>
> On 17/11/10 10:20, Superymk wrote:
> > So your point is the guest CR3 needs to be "extended" to 64 bits with
> > zeroes first, if it is a 32-bit guest. right?
> >
> > On 11/17/2010 6:11 PM, George Dunlap wrote:
> > > If you're in 64-bit mode and the hardware had a TLB miss for virtual
> > > address of 0xdeadb000, how would the hardware walk the pagetables?
> > > There are 20 bits for the virtual frame number, but each page-table
> > > entry has 9 bits.
> > >
> > > It's the exact same situation if the guest cr3 was set to 0xdeadb000.
> > > The indexes into the higher-level tables would simply be zero.
> > >
> > >    -George
> > >
> > > On Wed, Nov 17, 2010 at 9:40 AM, Superymk<superymkxen@xxxxxxxxxxx>   
> > > wrote:
> > > > Your figure points out the exactly EPT translation mechanism for an 
> > > > X64
> > > > guest.
> > > >
> > > > In the face of an X86_32 guest, how can EPT find the right EPML4 
> > > > entry when
> > > > translating CR3's pfn value into the right mfn value? There are 20 
> > > > bits for
> > > > indexing in total, while each level of EPT paging structure uses 
> > > > only 9 bits
> > > > for indexing.
> > > >
> > > >
> > > > On 11/17/2010 5:20 PM, Chu Rui wrote:
> > > >
> > > > Maybe this figure depicts the process...
> > > >
> > > > The original URL is http://software.intel.com/file/25040
> > > >
> > > > 2010/11/17 Superymk<superymkxen@xxxxxxxxxxx>
> > > > > Hi all,
> > > > >
> > > > > Can some one please tell me how EPT translates an X86_32 guest 
> > > > > physical
> > > > > address? I have read the Intel's manual, but it seems there is no 
> > > > > discussion
> > > > > about this condition.
> > > > >
> > > > > My concern is that, the guest CR3 pfn can be considered as being
> > > > > constituted by two 10 bits indexers for an X86_32 virtual machine. 
> > > > > However,
> > > > > the EPT paging structures is similar with the page tables used on 
> > > > > X86_64
> > > > > platform. which has four 9 bits indexers in its address layout. In 
> > > > > addition,
> > > > > each EPT entry is 64 bits long. Hence, a 4K page can hold at most 512
> > > > > entries. So, if the guest CR3's pfn is 0xfffff (an X86_32 virtual 
> > > > > machine)
> > > > > and I get a valid EPTP, how EPT will perform the translation?
> > > > >
> > > > > Thanks,
> > > > > Superymk
> > > > >
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