Re: [Xen-devel] How EPT translates an X86_32 guest physical address?

[Superymk <superymkxen@xxxxxxxxxxx>]

Your figure points out the exactly EPT translation mechanism for an X64 guest.

In the face of an X86_32 guest, how can EPT find the right EPML4 entry when translating CR3's pfn value into the right mfn value? There are 20 bits for indexing in total, while each level of EPT paging structure uses only 9 bits for indexing.


On 11/17/2010 5:20 PM, Chu Rui wrote:

Maybe this figure depicts the process...

 

The original URL is http://software.intel.com/file/25040

 

2010/11/17 Superymk <superymkxen@xxxxxxxxxxx>

Hi all,

Can some one please tell me how EPT translates an X86_32 guest physical address? I have read the Intel's manual, but it seems there is no discussion about this condition.

My concern is that, the guest CR3 pfn can be considered as being constituted by two 10 bits indexers for an X86_32 virtual machine. However, the EPT paging structures is similar with the page tables used on X86_64 platform. which has four 9 bits indexers in its address layout. In addition, each EPT entry is 64 bits long. Hence, a 4K page can hold at most 512 entries. So, if the guest CR3's pfn is 0xfffff (an X86_32 virtual machine) and I get a valid EPTP, how EPT will perform the translation?

Thanks,
Superymk

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