[XTF PATCH v1 14/15] x86: apic: add few more registers

[dmukhin@xxxxxxxx]

From: Denis Mukhin <dmukhin@xxxxxxxx>

Add few more registers definitions for testing: TPR, EOI, ISR, IRR.

Add routines to extract APIC ID from register 0x20.

Signed-off-by: Denis Mukhin <dmukhin@xxxxxxxx>
---
 arch/x86/include/arch/apic.h | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/arch/x86/include/arch/apic.h b/arch/x86/include/arch/apic.h
index 71c09a836998..8cf28ba5a39b 100644
--- a/arch/x86/include/arch/apic.h
+++ b/arch/x86/include/arch/apic.h
@@ -17,10 +17,24 @@
 
 /* Local APIC register definitions. */
 #define APIC_ID         0x020
+#define   GET_xAPIC_ID(x)         (((x) >> 24) & 0xffu)
+#define   SET_xAPIC_ID(x)         (((x) << 24))
+
 #define APIC_LVR        0x030
+
+#define APIC_TPR        0x080
+#define   APIC_TPR_MASK           0x000FF
+
+#define APIC_EOI        0x0b0
+#define   APIC_EOI_ACK            0x00000
+
 #define APIC_SPIV       0x0f0
 #define   APIC_SPIV_APIC_ENABLED  0x00100
 
+#define APIC_ISR        0x100
+
+#define APIC_IRR        0x200
+
 #define APIC_ESR        0x280
 #define   APIC_SIV                0x00020 /* Send Illegal Vector */
 #define   APIC_RIV                0x00040 /* Recieve Illegal Vector */
@@ -126,6 +140,21 @@ static inline void apic_icr_write(uint64_t val)
         return apic_msr_icr_write(val);
 }
 
+static inline bool apic_isr_read(unsigned int vector)
+{
+    return apic_read(APIC_ISR + (vector / 32 * 0x10)) & (1U << (vector % 32));
+}
+
+static inline bool apic_irr_read(unsigned int vector)
+{
+    return apic_read(APIC_IRR + (vector / 32 * 0x10)) & (1U << (vector % 32));
+}
+
+static inline unsigned int get_apic_id(void)
+{
+    return GET_xAPIC_ID(apic_read(APIC_ID));
+}
+
 #endif /* XTF_X86_APIC_H */
 
 /*
-- 
2.55.0