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Re: [PATCH] x86/pv: Improve code generation in async_exception_cleanup()
- To: Jan Beulich <jbeulich@xxxxxxxx>
- From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- Date: Wed, 4 Nov 2026 17:30:12 +0000
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- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Roger Pau Monné <roger@xxxxxxxxxxxxxx>, Teddy Astie <teddy.astie@xxxxxxxxxx>, Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- Delivery-date: Wed, 04 Nov 2026 17:31:33 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 03/11/2026 11:36 am, Jan Beulich wrote:
> On 03.11.2026 12:00, Andrew Cooper wrote:
>> On 02/11/2026 5:42 pm, Andrew Cooper wrote:
>>> Use new helper functions to simplfiy the logic. This removes an alternative
>>> behind the scenes.
> Does it? __scanbit() engages an alternative only when its 2nd argument is
> BITS_PER_LONG.
Oh, yes. I'll drop that sentence.
>>> No functional change.
>>>
>>> Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
>>> ---
>>> CC: Jan Beulich <jbeulich@xxxxxxxx>
>>> CC: Roger Pau Monné <roger@xxxxxxxxxxxxxx>
>>> CC: Teddy Astie <teddy.astie@xxxxxxxxxx>
>>>
>>> async_exception_cleanup() is complete nonsense. It's not remotely close to
>>> how interupt blocking works in x86.
> Are you perhaps expecting something that (for PV) was never intended?
I've long since given up being surprised at PV doing bizarre things.
This async_exception_state[].pending is used for HVM guests; this aspect
does need to change.
async_exception_state[].old_mask is specific to PV and, AFAICT,
interlocks both NMI and #MC together so they nest, with HYPERCALL_iret
"refcounts" the unwinding.
Architecturally, NMIs are blocked until the next sequential IRET, while
#MC has no blocking capabilities at all.
PV guests behaving the way they do violates the principle of least surprise.
>>> --- a/xen/arch/x86/pv/iret.c
>>> +++ b/xen/arch/x86/pv/iret.c
>>> @@ -31,8 +31,8 @@ static void async_exception_cleanup(struct vcpu *curr)
>>> if ( !curr->arch.async_exception_mask )
>>> return;
>>>
>>> - if ( !(curr->arch.async_exception_mask &
>>> (curr->arch.async_exception_mask - 1)) )
>>> - trap = __scanbit(curr->arch.async_exception_mask, VCPU_TRAP_NONE);
>>> + if ( !multiple_bits_set(curr->arch.async_exception_mask) )
>>> + trap = ffs(curr->arch.async_exception_mask) + 1;
>> This should of course be a -1 rather than +1. Fixed locally.
> Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
> (with the description corrected or you pointing out which other alternative
> you mean)
Thanks.
~Andrew
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