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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] [PATCH 6/6] treewide: Make {invalidate/clean}_dcahce_va_range() void
Precisely two functions - RISC-V's flush_page_to_ram() and ARM's
_cache_flush() - check the return value of these functions, yet all
implementations return success, and ARM documents this as a requirement.
Make them void and simply the callers which care.
No functional change.
Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
CC: Stefano Stabellini <sstabellini@xxxxxxxxxx>
CC: Julien Grall <julien@xxxxxxx>
CC: Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
CC: Bertrand Marquis <bertrand.marquis@xxxxxxx>
CC: Michal Orzel <michal.orzel@xxxxxxx>
CC: Jan Beulich <jbeulich@xxxxxxxx>
CC: Roger Pau Monné <roger@xxxxxxxxxxxxxx>
CC: Teddy Astie <teddy.astie@xxxxxxxxxx>
CC: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>
CC: Baptiste Le Duc <baptiste.le-duc@xxxxxxxxxx>
---
xen/arch/arm/include/asm/page.h | 20 +++++++-------------
xen/arch/riscv/include/asm/page.h | 10 +++-------
xen/arch/riscv/mm.c | 4 +---
xen/common/grant_table.c | 11 +++++------
4 files changed, 16 insertions(+), 29 deletions(-)
diff --git a/xen/arch/arm/include/asm/page.h b/xen/arch/arm/include/asm/page.h
index 6da4745736a2..b719c2ed4c12 100644
--- a/xen/arch/arm/include/asm/page.h
+++ b/xen/arch/arm/include/asm/page.h
@@ -165,13 +165,13 @@ static inline size_t read_dcache_line_bytes(void)
* if 'range' is large enough we might want to use model-specific
* full-cache flushes. */
-static inline int invalidate_dcache_va_range(const void *p, unsigned long size)
+static inline void invalidate_dcache_va_range(const void *p, unsigned long
size)
{
size_t cacheline_mask = dcache_line_bytes - 1;
unsigned long partial_head;
if ( !size )
- return 0;
+ return;
/* Passing a region that wraps around is illegal */
ASSERT(((uintptr_t)p + size - 1) >= (uintptr_t)p);
@@ -208,17 +208,15 @@ static inline int invalidate_dcache_va_range(const void
*p, unsigned long size)
done:
dsb(sy); /* So we know the flushes happen before continuing */
-
- return 0;
}
-static inline int clean_dcache_va_range(const void *p, unsigned long size)
+static inline void clean_dcache_va_range(const void *p, unsigned long size)
{
size_t cacheline_mask = dcache_line_bytes - 1;
unsigned long idx = 0;
if ( !size )
- return 0;
+ return;
/* Passing a region that wraps around is illegal */
ASSERT(((uintptr_t)p + size - 1) >= (uintptr_t)p);
@@ -231,18 +229,16 @@ static inline int clean_dcache_va_range(const void *p,
unsigned long size)
idx += dcache_line_bytes, size -= dcache_line_bytes )
asm_inline volatile ( __clean_dcache_one(0) : : "r" (p + idx) );
dsb(sy); /* So we know the flushes happen before continuing */
- /* ARM callers assume that dcache_* functions cannot fail. */
- return 0;
}
-static inline int clean_and_invalidate_dcache_va_range
- (const void *p, unsigned long size)
+static inline void
+clean_and_invalidate_dcache_va_range(const void *p, unsigned long size)
{
size_t cacheline_mask = dcache_line_bytes - 1;
unsigned long idx = 0;
if ( !size )
- return 0;
+ return;
/* Passing a region that wraps around is illegal */
ASSERT(((uintptr_t)p + size - 1) >= (uintptr_t)p);
@@ -255,8 +251,6 @@ static inline int clean_and_invalidate_dcache_va_range
idx += dcache_line_bytes, size -= dcache_line_bytes )
asm volatile (__clean_and_invalidate_dcache_one(0) : : "r" (p + idx));
dsb(sy); /* So we know the flushes happen before continuing */
- /* ARM callers assume that dcache_* functions cannot fail. */
- return 0;
}
/* Macros for flushing a single small item. The predicate is always
diff --git a/xen/arch/riscv/include/asm/page.h
b/xen/arch/riscv/include/asm/page.h
index f9e59e61de30..770410085fd9 100644
--- a/xen/arch/riscv/include/asm/page.h
+++ b/xen/arch/riscv/include/asm/page.h
@@ -196,23 +196,19 @@ static inline bool pte_is_superpage(pte_t p, unsigned int
level)
return (level > 0) && pte_is_mapping(p);
}
-static inline int clean_and_invalidate_dcache_va_range(const void *p,
- unsigned long size)
+static inline void
+clean_and_invalidate_dcache_va_range(const void *p, unsigned long size)
{
#ifndef CONFIG_QEMU_PLATFORM
# error "should clean_and_invalidate_dcache_va_range() be updated?"
#endif
-
- return 0;
}
-static inline int clean_dcache_va_range(const void *p, unsigned long size)
+static inline void clean_dcache_va_range(const void *p, unsigned long size)
{
#ifndef CONFIG_QEMU_PLATFORM
# error "should clean_dcache_va_range() be updated?"
#endif
-
- return 0;
}
static inline void invalidate_icache(void)
diff --git a/xen/arch/riscv/mm.c b/xen/arch/riscv/mm.c
index 6f7dcd10b2c6..78f23392cc35 100644
--- a/xen/arch/riscv/mm.c
+++ b/xen/arch/riscv/mm.c
@@ -618,9 +618,7 @@ void flush_page_to_ram(unsigned long mfn, bool sync_icache)
{
const void *v = map_domain_page(_mfn(mfn));
- if ( clean_and_invalidate_dcache_va_range(v, PAGE_SIZE) )
- BUG();
-
+ clean_and_invalidate_dcache_va_range(v, PAGE_SIZE);
unmap_domain_page(v);
if ( sync_icache )
diff --git a/xen/common/grant_table.c b/xen/common/grant_table.c
index d453c38556fc..eebf8850d062 100644
--- a/xen/common/grant_table.c
+++ b/xen/common/grant_table.c
@@ -3673,14 +3673,13 @@ static int _cache_flush(gnttab_cache_flush_t *cflush,
grant_ref_t *cur_ref)
v = map_domain_page(mfn);
v += cflush->offset;
+ ret = 0;
if ( (cflush->op & GNTTAB_CACHE_INVAL) && (cflush->op &
GNTTAB_CACHE_CLEAN) )
- ret = clean_and_invalidate_dcache_va_range(v, cflush->length);
+ clean_and_invalidate_dcache_va_range(v, cflush->length);
else if ( cflush->op & GNTTAB_CACHE_INVAL )
- ret = invalidate_dcache_va_range(v, cflush->length);
- else if ( cflush->op & GNTTAB_CACHE_CLEAN )
- ret = clean_dcache_va_range(v, cflush->length);
- else
- ret = 0;
+ invalidate_dcache_va_range(v, cflush->length);
+ else /* cflush->op & GNTTAB_CACHE_CLEAN */
+ clean_dcache_va_range(v, cflush->length);
unmap_domain_page(v);
--
2.39.5
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