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Re: [PATCH 1/2] x86/cpu: keep cached TSC_AUX state coherent with hardware
- To: Roger Pau Monne <roger@xxxxxxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxxx
- From: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
- Date: Mon, 2 Nov 2026 11:51:32 +0000
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- Cc: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Jan Beulich <jbeulich@xxxxxxxx>, Teddy Astie <teddy.astie@xxxxxxxxxx>
- Delivery-date: Mon, 02 Nov 2026 11:51:47 +0000
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
On 30/10/2026 1:24 pm, Roger Pau Monne wrote:
> On CPU bringup don't assume that TSC_AUX is 0, write 0 to it to ensure the
> per-CPU cached state matches the hardware. Also propagate the cached value
> on resume from suspend, in case the register value has been reset during
> suspension.
>
> Fixes: cc0e45db2779 ("x86/pv: Avoid leaking other guests' MSR_TSC_AUX values
> into PV context")
> Signed-off-by: Roger Pau Monné <roger@xxxxxxxxxxxxxx>
> ---
> xen/arch/x86/acpi/power.c | 3 +++
> xen/arch/x86/cpu/common.c | 5 +++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/xen/arch/x86/acpi/power.c b/xen/arch/x86/acpi/power.c
> index 3452650a61d5..464846e73727 100644
> --- a/xen/arch/x86/acpi/power.c
> +++ b/xen/arch/x86/acpi/power.c
> @@ -279,6 +279,9 @@ static int enter_state(u32 state)
> ci->last_spec_ctrl = default_xen_spec_ctrl;
> }
>
> + if ( cpu_has_msr_tsc_aux )
> + wrmsrns(MSR_TSC_AUX, this_cpu(tsc_aux));
> +
This wants to be later, with percpu_traps_init(). It is not critical
state to restore this early.
~Andrew
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