[PATCH 1/2] x86/cpu: keep cached TSC_AUX state coherent with hardware

[Roger Pau Monne <roger@xxxxxxxxxxxxxx>]

On CPU bringup don't assume that TSC_AUX is 0, write 0 to it to ensure the
per-CPU cached state matches the hardware.  Also propagate the cached value
on resume from suspend, in case the register value has been reset during
suspension.

Fixes: cc0e45db2779 ("x86/pv: Avoid leaking other guests' MSR_TSC_AUX values 
into PV context")
Signed-off-by: Roger Pau Monné <roger@xxxxxxxxxxxxxx>
---
 xen/arch/x86/acpi/power.c | 3 +++
 xen/arch/x86/cpu/common.c | 5 +++++
 2 files changed, 8 insertions(+)

diff --git a/xen/arch/x86/acpi/power.c b/xen/arch/x86/acpi/power.c
index 3452650a61d5..464846e73727 100644
--- a/xen/arch/x86/acpi/power.c
+++ b/xen/arch/x86/acpi/power.c
@@ -279,6 +279,9 @@ static int enter_state(u32 state)
         ci->last_spec_ctrl = default_xen_spec_ctrl;
     }
 
+    if ( cpu_has_msr_tsc_aux )
+        wrmsrns(MSR_TSC_AUX, this_cpu(tsc_aux));
+
     update_mcu_opt_ctrl();
     update_pb_opt_ctrl();
 
diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c
index 43785d19cc73..5beae0e87f49 100644
--- a/xen/arch/x86/cpu/common.c
+++ b/xen/arch/x86/cpu/common.c
@@ -926,6 +926,11 @@ void cpu_init(void)
 
        /* Enable NMIs.  Our loader (e.g. Tboot) may have left them disabled. */
        enable_nmis();
+
+       if (cpu_has_msr_tsc_aux) {
+               wrmsrns(MSR_TSC_AUX, 0);
+               this_cpu(tsc_aux) = 0;
+       }
 }
 
 void cpu_uninit(unsigned int cpu)
-- 
2.55.0