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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [PATCH v8 4/5] xen/riscv: probe the A/D update scheme if the DT advertises neither
On 10/26/26 5:59 PM, Jan Beulich wrote: On 26.10.2026 16:35, Oleksii Kurochko wrote:On 10/26/26 4:14 PM, Baptiste Le Duc wrote:+/* + * Probe whether hardware updates the PTE A/D bits by writing to a local + * variable through an alias mapping whose A and D bits are clear. + * + * Check the D bit rather than the A bit, as the A bit may be set + * speculatively while the D bit can't.Following Andrew's clarification, I don't think this is relevant anymore (but I also don't mind it to stay the way it is): If we observed the A bit set (and no fault), we can still deduce Svadu, no matter whether the update was due to an architectural or a speculative access. Svade would implicitly disallow speculative updates of A, as exceptions may only be raised for architectural accesses (unless there are provisions in the spec that I'm unaware of). Both of you: Please clarify whether you want this change to go in as-is, or whether this wants updating again. I'd prefer to update it: the statement itself is true, but it isn't a reason to check D rather than A, since, as you say, observing A set without a fault would equally imply Svadu. If you're fine adjusting it while committing, the second paragraph could become: Check the D bit, as it is set only once the store through the alias has been performed.(or just be dropped), with the matching sentence in the description ("The D bit is checked rather than the A bit, as the A bit may be set speculatively.") dropped as well. Otherwise Baptiste, please send an updated version. ~ Oleksii Generally, looks good to me: Reviewed-by: Oleksii Kurochko <oleksii.kurochko@xxxxxxxxx>Acked-by: Jan Beulich <jbeulich@xxxxxxxx>
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