[PATCH v2] x86/vlapic: Don't change ICR on x2APIC SELF_IPI write

[Teddy Astie <teddy.astie@xxxxxxxxxx>]

The Intel SDM (Vol 3A-13.12.11, June 2026) says

> The semantics of sending a self-IPI via the SELF IPI register
> are identical to sending a self targeted edge triggered fixed
> interrupt with the specified vector.

However, this doesn't require altering the ICR register.
On most Intel processors (at least Core/P-Core), it does alter ICR,
but it's not the case on AMD and Atom/E-Core ones, and APICv Self-IPI
appears to follow a similar behavior.

For consistency, adjust the Xen behavior to send the Self-IPI
directly instead of emulating it by modifying ICR register.

It also clarify the logic.

Assisted-by: Claude Fable 5.1
Signed-off-by: Teddy Astie <teddy.astie@xxxxxxxxxx>
---
I haven't check if APICv Self-IPI doesn't alter the ICR, this is
mostly based on what suggest Andrew's comment [1]. Intel SDM doesn't
actually tell much if ICR is modified by APICv Self-IPI but
behavior pseudo-code suggest that ICR is not considered at all,
hence Self-IPI is done differently.

[1] 
https://lore.kernel.org/xen-devel/b236e564-c2fd-44d1-93ee-8bb87e2e2c0f@xxxxxxxxxx/

v2:
 - adjust commit message, drop Fixes
 - drop vlapic_self_ipi() function
 - reorganize vlapic_apicv_write()
---
 xen/arch/x86/hvm/vlapic.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/xen/arch/x86/hvm/vlapic.c b/xen/arch/x86/hvm/vlapic.c
index 885f5d304b..7d6b1a6e0d 100644
--- a/xen/arch/x86/hvm/vlapic.c
+++ b/xen/arch/x86/hvm/vlapic.c
@@ -970,11 +970,13 @@ int vlapic_apicv_write(struct vcpu *v, unsigned int 
offset)
 
     if ( vlapic_x2apic_mode(vlapic) )
     {
-        if ( offset != APIC_SELF_IPI )
-            return X86EMUL_UNHANDLEABLE;
+        if ( offset == APIC_SELF_IPI )
+        {
+            vlapic_ipi(vlapic, APIC_DEST_SELF | (val & APIC_VECTOR_MASK), 0);
+            return X86EMUL_OKAY;
+        }
 
-        offset = APIC_ICR;
-        val = APIC_DEST_SELF | (val & APIC_VECTOR_MASK);
+        return X86EMUL_UNHANDLEABLE;
     }
 
     vlapic_reg_write(v, offset, val);
@@ -1050,9 +1052,8 @@ int guest_wrmsr_x2apic(struct vcpu *v, uint32_t msr, 
uint64_t val)
     case APIC_SELF_IPI:
         if ( val & ~APIC_VECTOR_MASK )
             return X86EMUL_EXCEPTION;
-        offset = APIC_ICR;
-        val = APIC_DEST_SELF | (val & APIC_VECTOR_MASK);
-        break;
+        vlapic_ipi(vlapic, APIC_DEST_SELF | (val & APIC_VECTOR_MASK), 0);
+        return X86EMUL_OKAY;
 
     case APIC_EOI:
     case APIC_ESR:
-- 
2.56.0



--
Teddy Astie | Vates XCP-ng Developer

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