[PATCH 0/6] vmx/apicv: APICv and IOMMU posted interrupt improvements

[Teddy Astie <teddy.astie@xxxxxxxxxx>]

Various improvements around APICv/iommu-intpost found by Claude Fable
(and Opus).

Some of the APICv bugfixes makes APICv behavior align better with
emulated lapic.

Testing shows that "Don't lose posted interrupts while SN=1" vastly
improves VT-d interrupt posting reliability.
I guess there's more stuff to fix (especially around comments), but
that's probably a good start.

I'm not sure how the current HVM infra around interrupt posting
fits with AMD AVIC. Feedback welcome.

Teddy Astie (6):
  vmx/apicv: Fix vmx_pi_hooks_assign() comment
  x86/vlapic: Fix hardware virtualized APIC state after reset
  vmx/apicv: Don't lose posted interrupts while SN=1
  vmx/apicv: Fully deassign the PI hooks when the last device is removed
  vmx/apicv: Replace the PI_CSW_{FROM,TO} flags with a boolean
  vmx/apicv: Don't defer RVI update when an event is pending injection

 xen/arch/x86/hvm/vlapic.c              |  43 ++++++-
 xen/arch/x86/hvm/vmx/intr.c            |  11 +-
 xen/arch/x86/hvm/vmx/vmx.c             | 159 ++++++++++++++++---------
 xen/arch/x86/include/asm/hvm/domain.h  |   3 +-
 xen/arch/x86/include/asm/hvm/vmx/vmx.h |   5 +
 5 files changed, 160 insertions(+), 61 deletions(-)

-- 
2.56.0



--
Teddy Astie | Vates XCP-ng Developer

XCP-ng & Xen Orchestra - Vates solutions

web: https://vates.tech