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[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index] Re: [PATCH 15/28] hw: define most common PCI types as secure
On Fri, Sep 11, 2026 at 03:36:14PM +0100, Daniel P. Berrangé wrote:
> Essentially all PCI infrastructure is in scope for the virtualization
> use case, aside from the niche simba bridge.
>
> Signed-off-by: Daniel P. Berrangé <berrange@xxxxxxxxxx>
> ---
> hw/pci-bridge/gen_pcie_root_port.c | 1 +
> hw/pci-bridge/i82801b11.c | 1 +
> hw/pci-bridge/ioh3420.c | 1 +
> hw/pci-bridge/pci_bridge_dev.c | 2 ++
> hw/pci-bridge/pci_expander_bridge.c | 8 ++++++++
> hw/pci-bridge/pcie_pci_bridge.c | 1 +
> hw/pci-bridge/pcie_root_port.c | 1 +
> hw/pci-bridge/xio3130_downstream.c | 1 +
> hw/pci-bridge/xio3130_upstream.c | 1 +
> hw/pci/pci.c | 7 +++++++
> hw/pci/pci_bridge.c | 1 +
> hw/pci/pci_host.c | 1 +
> hw/pci/pcie_host.c | 1 +
> hw/pci/pcie_port.c | 1 +
> 14 files changed, 28 insertions(+)
>
> diff --git a/hw/pci-bridge/pci_expander_bridge.c
> b/hw/pci-bridge/pci_expander_bridge.c
> index 40ffbc4e08..bd5598b639 100644
> --- a/hw/pci-bridge/pci_expander_bridge.c
> +++ b/hw/pci-bridge/pci_expander_bridge.c
snip
> @@ -128,6 +130,7 @@ static const TypeInfo pxb_cxl_bus_info = {
> .parent = TYPE_CXL_BUS,
> .instance_size = sizeof(PXBBus),
> .class_init = pxb_bus_class_init,
> + .secure = true,
> };
>
snip
> static void pxb_cxl_realize(DeviceState *dev, Error **errp)
> @@ -249,6 +253,7 @@ static const TypeInfo cxl_host_info = {
> .parent = TYPE_PCI_HOST_BRIDGE,
> .instance_size = sizeof(CXLHost),
> .class_init = pxb_cxl_host_class_init,
> + .secure = true,
> };
>
> /*
snip
> @@ -540,6 +547,7 @@ static const TypeInfo pxb_cxl_dev_info = {
> .parent = TYPE_PXB_PCIE_DEV,
> .instance_size = sizeof(PXBCXLDev),
> .class_init = pxb_cxl_dev_class_init,
> + .secure = true,
> .interfaces =
> (const InterfaceInfo[]){
> { INTERFACE_CONVENTIONAL_PCI_DEVICE },
These three were a mistake. No CXL code is intended to be classed as
secure at this time.
With regards,
Daniel
--
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