[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[PATCH v2 2/3] xen/arm: vgic: free eSPIs using the bitmap index


  • To: xen-devel@xxxxxxxxxxxxxxxxxxxx
  • From: Mykola Kvach <mykola_kvach@xxxxxxxx>
  • Date: Mon, 10 Aug 2026 21:38:46 +0300
  • Arc-authentication-results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=epam.com; dmarc=pass action=none header.from=epam.com; dkim=pass header.d=epam.com; arc=none
  • Arc-message-signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3oS5+tMpm/5iXbHipLKgLe69zKs89CKb5K72EOJFaZw=; b=m7QzPTf1vCaIA+54KwKVqE0+fOyBelUiQ0wdpRCjmREd3E662KF29u+zkjy2dR5OgYf54WCDOz/ytpdG8FUUkAbvXLsCRF5uXwMIQkjfcd7ZCyd2W++UnTqe9BYO8MEjg1sbmPYtf8aY5GSMjW6lXDbAvc+qBBMTg1+aAL7FOBhNe1nj8lLt7EeRXc+v4UW8ENkcAam5Y0HErWOjic5jGmL3Io/dfFId+2DP1bNh5tmUJd47/TUKYY8mm1AwyGQnpj0HIyeYyC2OW7n67hVffbBBVVr5MNPhg15QRRCERfQZxZI4th1JUdx9k1r0jxszBfyktpr7MBvT5SKlc8rhIw==
  • Arc-seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Q5uBXhzZOluqHZr0P63zd2MnW5MM1HybjByZYGeEQdeVkyWY0vTsEjGbHm3nyJOBdXm5eGKZ4O9VptcC7UF50wGYPDvtDIywmSS2djXXY2/QUdu6XlGspGkE9Q9LxLMM+DCkQ1NnjZE7PzNITArbjH5Btp/U3ZRXNxcvwlVxpM63sLZ7ppSkrreQkmVhH0IJocjqXgIlEvgC6IBYk2NCymoMGGhSQzdqkc58D7IwN6S5cB9vwDtlLPmZSO2fNakfGf8bhC5DW0OgcboVoDPimEbNucdpcj3HkcOrOlnB7Xgp/jU5muGz8tYO1yxLTV7En8+MvgWHhAz1rSSgYkxocw==
  • Authentication-results: eu.smtp.expurgate.cloud; dkim=pass header.s=selector1 header.d=epam.com header.i="@epam.com" header.h="From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck"
  • Authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=epam.com;
  • Cc: Stefano Stabellini <sstabellini@xxxxxxxxxx>, Julien Grall <julien@xxxxxxx>, Bertrand Marquis <bertrand.marquis@xxxxxxx>, Michal Orzel <michal.orzel@xxxxxxx>, Volodymyr Babchuk <Volodymyr_Babchuk@xxxxxxxx>
  • Delivery-date: Mon, 10 Aug 2026 18:39:15 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

The allocated_irqs bitmap in the existing vGIC implementation stores eSPI
allocation bits immediately after the regular vIRQ bits.
vgic_reserve_virq() converts an eSPI INTID to this compressed bitmap index,
but vgic_free_virq() used the raw INTID.

Freeing INTID 4096 therefore clears bit 4096 instead of the first eSPI bit.
This writes beyond allocated_irqs and leaves the intended eSPI bit set.
Valid eSPIs reach this path during DOMCTL bind failure cleanup and unbind,
and during vPL011 teardown.

Add virq_to_idx(), the inverse of idx_to_virq(), and use it when reserving
and freeing vIRQs. Validate a vIRQ before clearing its allocation bit.

Fixes: bdde400c6e1b ("xen/arm: vgic: add resource management for extended SPIs")
Signed-off-by: Mykola Kvach <mykola_kvach@xxxxxxxx>
---
Changes in v2:
- Call is_espi() without a configuration guard.
---
 xen/arch/arm/vgic.c | 25 ++++++++++++++-----------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c
index e5aca17dcb..c095866709 100644
--- a/xen/arch/arm/vgic.c
+++ b/xen/arch/arm/vgic.c
@@ -33,6 +33,14 @@ static inline unsigned int idx_to_virq(struct domain *d, 
unsigned int idx)
     return idx;
 }
 
+static inline unsigned int virq_to_idx(struct domain *d, unsigned int virq)
+{
+    if ( is_espi(virq) )
+        return espi_intid_to_idx(virq) + vgic_num_irqs(d);
+
+    return virq;
+}
+
 bool vgic_is_valid_line(struct domain *d, unsigned int virq)
 {
 #ifdef CONFIG_GICV3_ESPI
@@ -848,19 +856,11 @@ bool vgic_emulate(struct cpu_user_regs *regs, union hsr 
hsr)
 
 bool vgic_reserve_virq(struct domain *d, unsigned int virq)
 {
-    unsigned int idx = virq;
-
     if ( !vgic_is_valid_line(d, virq) )
         return false;
 
-    if ( is_espi(virq) )
-    {
-        unsigned int num_regular_irqs = vgic_num_irqs(d);
-
-        idx = espi_intid_to_idx(virq) + num_regular_irqs;
-    }
-
-    return !test_and_set_bit(idx, d->arch.vgic.allocated_irqs);
+    return !test_and_set_bit(virq_to_idx(d, virq),
+                             d->arch.vgic.allocated_irqs);
 }
 
 int vgic_allocate_virq(struct domain *d, bool spi)
@@ -897,7 +897,10 @@ int vgic_allocate_virq(struct domain *d, bool spi)
 
 void vgic_free_virq(struct domain *d, unsigned int virq)
 {
-    clear_bit(virq, d->arch.vgic.allocated_irqs);
+    if ( !vgic_is_valid_line(d, virq) )
+        return;
+
+    clear_bit(virq_to_idx(d, virq), d->arch.vgic.allocated_irqs);
 }
 
 unsigned int vgic_max_vcpus(unsigned int domctl_vgic_version)
-- 
2.43.0




 


Rackspace

Lists.xenproject.org is hosted with RackSpace, monitoring our
servers 24x7x365 and backed by RackSpace's Fanatical Support®.