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Re: [PATCH v2] nSVM: Check injected event consistency


  • To: Abdelkareem Abdelsaamad <abdelkareem.abdelsaamad@xxxxxxxxxx>
  • From: Jan Beulich <jbeulich@xxxxxxxx>
  • Date: Mon, 3 Aug 2026 09:12:05 +0200
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  • Cc: andrew.cooper3@xxxxxxxxxx, Roger Pau Monné <roger@xxxxxxxxxxxxxx>, jason.andryuk@xxxxxxx, xen-devel@xxxxxxxxxxxxxxxxxxxx, teddy.astie@xxxxxxxxxx
  • Delivery-date: Mon, 03 Aug 2026 07:12:17 +0000
  • List-id: Xen developer discussion <xen-devel.lists.xenproject.org>

On 31.07.2026 16:26, Abdelkareem Abdelsaamad wrote:
> On 28.07.2026 14:04, Teddy Astie wrote:
>> On 16.07.2026 17:41, Abdelkareem Abdelsaamad wrote:
>>> --- a/xen/arch/x86/hvm/svm/vmcb.c
>>> +++ b/xen/arch/x86/hvm/svm/vmcb.c
>>> @@ -320,6 +320,31 @@ void svm_vmcb_dump(const char *from, const struct 
>>> vmcb_struct *vmcb)
>>>       svm_dump_sel("  TR", &vmcb->tr);
>>>   }
>>>   
>>> +static bool is_valid_svm_vmcb_injected_exception_vector(
>>> +    const struct vmcb_struct *vmcb, uint8_t vmcb_injected_vector)
>>> +{
>>> +    return ( (vmcb_injected_vector == X86_EXC_DE) ||
>>> +             (vmcb_injected_vector == X86_EXC_DB) ||
>>> +             (vmcb_injected_vector == X86_EXC_BP) ||
>>> +             (vmcb_injected_vector == X86_EXC_OF) ||
>>> +             (vmcb_injected_vector == X86_EXC_BR) ||
>>
>> This particular exception is special. AMD APM states that this event is 
>> "impossible" if the guest is in 64-bit mode and will cause 
>> VMEXIT_INVALID in such case.
>>
>>> If the VMM attempts to inject an event that is impossible for the 
>> guest mode (e.g., a #BR exception when the guest is in 64-bit mode), the 
>> event injection will fail and no guest state instructions will be 
>> executed; VMRUN will immediately exit with an error code of VMEXIT_INVALID.
>>
>> So this one likely want a additional check for hvm_guest_x86_mode() != 
>> X86_MODE_64BIT.
>>
>> It looks like #OF has the same quirk (invalid in 64-bits mode).
>>
> I agree your point is valid. I will address in V3.
>> Though I don't know if any other exception has a similar behavior though.
> I have double-checked the APM vOL3(24594—Rev. 3.37—jULY 2025) regarding the
> other exception vectors and instructions. Vector 4 (#OF) and vector 5 (#BR) 
> are
> unique because their triggering instructions BOUND and INTO are invalid and
> disabled in 64-bit mode, making them structurally invalid. Other vectors 
> remain
> legal across the other modes.

#BR is also used by MPX insns, which are usable from 64-bit mode.

Jan



 


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