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Re: [PATCH v3] x86/emul: Adjust handling of CR8_LEGACY
- To: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>, Xen-devel <xen-devel@xxxxxxxxxxxxxxxxxxxx>
- From: Teddy Astie <teddy.astie@xxxxxxxxxx>
- Date: Wed, 8 Jul 2026 11:29:32 +0200
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- Cc: Jan Beulich <jbeulich@xxxxxxxx>, Roger Pau Monné <roger.pau@xxxxxxxxxx>
- Delivery-date: Wed, 08 Jul 2026 09:29:46 +0000
- Feedback-id: default:8631fc262581453bbf619ec5b2062170:Sweego
- List-id: Xen developer discussion <xen-devel.lists.xenproject.org>
Le 07/07/2026 à 21:49, Andrew Cooper a écrit :
The APM description of the AltMovCR8 feature bit is:
"LOCK MOV CR0 means MOV CR8"
Adjust the decode logic to behave like this.
Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
---
CC: Jan Beulich <jbeulich@xxxxxxxx>
CC: Roger Pau Monné <roger.pau@xxxxxxxxxx>
CC: Teddy Astie <teddy.astie@xxxxxxxxxx>
v3:
* Change yet again. A contact with information on the matter confirmed that
it is a special case for Reg = 0, and not a general modifier to all Reg
values.
---
xen/arch/x86/x86_emulate/decode.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/xen/arch/x86/x86_emulate/decode.c
b/xen/arch/x86/x86_emulate/decode.c
index 2c13356c4d17..57f6baffb066 100644
--- a/xen/arch/x86/x86_emulate/decode.c
+++ b/xen/arch/x86/x86_emulate/decode.c
@@ -780,12 +780,12 @@ decode_twobyte(struct x86_emulate_state *s,
break;
case 0x20: case 0x22: /* mov to/from cr */
- if ( s->lock_prefix && vcpu_has_cr8_legacy() )
+ if ( s->lock_prefix && vcpu_has_cr8_legacy() && s->modrm_reg == 0 )
{
- s->modrm_reg += 8;
+ s->modrm_reg = 8;
s->lock_prefix = false;
}
- /* fall through */
+ fallthrough;
case 0x21: case 0x23: /* mov to/from dr */
ASSERT(s->ea.type == OP_REG); /* Early operand adjustment ensures
this. */
generate_exception_if(s->lock_prefix, X86_EXC_UD);
I'm fine with it; though we probably want to make sure we always
advertise the AltMovCr8 feature bit as APM suggest users to always check
for this before relying on this behavior.
Interestingly, I see this feature bit set on Intel hardware.
Though, it's a reserved bit in SDM, and lock mov cr0 is defined as being
#UD.
Which CPU model introduced this feature bit ? And does Intel behavior
matches AMD's spec ?
Teddy
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